Anand270294 / AES-encryption-VSLI
EE4415 Project : AES Verilog
☆9Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for AES-encryption-VSLI
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆19Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- ☆16Updated 10 months ago
- ☆16Updated 7 months ago
- SystemVerilog examples and projects☆17Updated 6 years ago
- Architectural design of data router in verilog☆27Updated 4 years ago
- ☆40Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- PCIE 5.0 Graduation project (Verification Team)☆55Updated 9 months ago
- ☆36Updated 3 years ago
- AXI Interconnect☆46Updated 3 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- ☆13Updated 8 months ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆20Updated 2 years ago
- Maven Silicon Project☆18Updated 6 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- ☆10Updated last year
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆16Updated 3 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆53Updated last year
- UVM Testbench to verify serial transmission of data between SPI master and slave☆34Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆71Updated last year
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆12Updated last year
- UART design in SV and verification using UVM and SV☆37Updated 4 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆35Updated 5 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆27Updated last year
- An 8 input interrupt controller written in Verilog.☆25Updated 12 years ago
- Verification IP for APB protocol☆56Updated 3 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 5 years ago
- IEEE Executive project for the year 2021-2022☆8Updated 2 years ago