NingHeChuan / Open-FPGA
Devotes to open source FPGA
☆28Updated 4 years ago
Alternatives and similar repositories for Open-FPGA:
Users that are interested in Open-FPGA are comparing it to the libraries listed below
- Verilog极简教程☆36Updated 6 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- ☆31Updated 3 weeks ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆126Updated 5 years ago
- ☆23Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆60Updated last year
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆103Updated 2 years ago
- Cortex M0 based SoC☆71Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- VSCode extension for enhancing verilog☆24Updated 11 months ago
- ☆65Updated 2 years ago
- FFT generator using Chisel☆58Updated 3 years ago
- Build an open source, extremely simple DMA.☆21Updated 6 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆52Updated 9 months ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆114Updated 2 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆64Updated 4 months ago
- SDRAM controller with AXI4 interface☆89Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- Gaussian noise generator Verilog IP core☆30Updated last year
- Verilog SPI master and slave☆52Updated 9 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆23Updated last year
- a super-simple pipelined verilog divider. flexible to define stages☆54Updated 5 years ago
- ☆57Updated 2 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- DDR4 Simulation Project in System Verilog☆38Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Light-weight RISC-V RV32IMC microcontroller core.☆104Updated 8 years ago