zhhangBian / BOOM_chipLinks
乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四
☆14Updated 10 months ago
Alternatives and similar repositories for BOOM_chip
Users that are interested in BOOM_chip are comparing it to the libraries listed below
Sorting:
- ☆72Updated 2 months ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆29Updated 2 years ago
- ☆86Updated last month
- ☆68Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆66Updated 10 months ago
- ☆24Updated 2 months ago
- Open IP in Hardware Description Language.☆24Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 2 years ago
- This is my graduation project, a simple processor soft core, which implements RV32I ISA.☆17Updated 6 years ago
- A RISC-V RV32I ISA Single Cycle CPU☆24Updated last month
- 关于移植模型至gemmini的文档☆27Updated 3 years ago
- ☆18Updated 2 years ago
- A framework for ysyx flow☆11Updated 7 months ago
- ☆68Updated 4 months ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆55Updated last year
- Documentation for XiangShan Design☆27Updated 3 weeks ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- ☆42Updated 3 years ago
- 一生一芯RISCV处理器核代码仓库(包括相关工具)☆14Updated 9 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 2 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆13Updated 2 months ago
- CPU Design Based on RISCV ISA☆113Updated last year
- ☆19Updated 10 months ago
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆20Updated 7 months ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- Build mini linux for your own RISC-V emulator!☆21Updated 9 months ago
- ☆51Updated 6 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- ☆64Updated 2 years ago