Clo91eaf / PUA-MIPSLinks
NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
☆13Updated 9 months ago
Alternatives and similar repositories for PUA-MIPS
Users that are interested in PUA-MIPS are comparing it to the libraries listed below
Sorting:
- Build mini linux for your own RISC-V emulator!☆24Updated last year
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛(龙芯杯)团队赛二等奖作品☆21Updated last year
- 适用于龙芯杯团队赛入门选手的应急cache模块☆30Updated last year
- ☆67Updated last year
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Updated 3 weeks ago
- "aura" my super-scalar O3 cpu core☆24Updated last year
- ☆29Updated 11 months ago
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆41Updated 5 years ago
- ☆35Updated 2 years ago
- ☆36Updated 5 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆193Updated last year
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆146Updated last year
- 给NEMU移植Linux Kernel!☆22Updated 7 months ago
- ☆89Updated 2 months ago
- ☆20Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Updated 9 months ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- Documentation for XiangShan Design☆39Updated this week
- ☆21Updated 7 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆22Updated 10 months ago
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆25Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- ☆91Updated 3 months ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆70Updated 11 months ago
- CPU敏捷开发框架(龙芯杯2024)☆25Updated last year
- A Study of the SiFive Inclusive L2 Cache☆70Updated 2 years ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆19Updated last year
- ☆64Updated 2 weeks ago