TianhuaTao / uCore-SMP

Related projects ⓘ

Alternatives and complementary repositories for uCore-SMP

• js2xxx / umi
  An RISC-V experimental OS
  ☆25Updated last year
• chyyuu / zCore-Design
  ☆13Updated 3 years ago
• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated last year
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 3 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆50Updated 11 months ago
• chenzhiy2001 / code-debug
  支持Rust语言的源代码级操作系统调试工具
  ☆34Updated 3 weeks ago
• luojia65 / tiaoshi-dashi-sbi
  调试大师：你见过最强的内核调试器
  ☆35Updated 3 years ago
• HUST-OS / design-pattern-notes
  各类内核的设计思路
  ☆19Updated 3 years ago
• YdrMaster / fast-trap
  快速陷入处理
  ☆32Updated last year
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆11Updated last week
• rcore-os / rcore-user
  User programs for rCore OS
  ☆18Updated 2 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• KuangjuX / hypocaust
  hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.
  ☆44Updated last year
• ring00 / bbl-ucore
  uCore OS Labs on Berkeley bootloader
  ☆39Updated 6 years ago
• xiyurain / UltraOS
  A Rust based Multicore OS developed by UltraTeam, HITsz. Currently updated on https://gitee.com/LoanCold/ultraos_backup
  ☆45Updated 5 months ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 2 years ago
• rustsbi / sbi-rt
  Simple RISC-V SBI runtime library; designated for supervisor use
  ☆21Updated 10 months ago
• IPADS-DuVisor / kvm-tutorial
  ☆22Updated last year
• ISRC-CAS / tarsier-oerv
  Project magament for porting openEuler to RISC-V
  ☆33Updated last year
• luojia65 / DailySchedule
  ☆22Updated 2 years ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 4 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆33Updated 3 years ago
• ksco / chibicc-riscv
  A fork of chibicc ported to RISC-V assembly.
  ☆38Updated 2 years ago
• MaxXSoft / GeeOS
  The Gee (寂) Operating System, written in YuLang.
  ☆34Updated 3 years ago
• OS-F-4 / usr-intr
  项目的主仓库
  ☆22Updated 2 years ago
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆30Updated 11 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆10Updated 7 months ago
• siriusdemon / Rare
  Build your own Riscv Emulator in Rust.
  ☆105Updated 2 years ago