Alternatives and similar repositories for uCore-SMP:

Users that are interested in uCore-SMP are comparing it to the libraries listed below

• rustsbi / rustsbi-hifive-unmatched
  RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core
  ☆17Updated last year
• js2xxx / umi
  An RISC-V experimental OS
  ☆25Updated last year
• oscomp / proj23-lightweight-hypervisor
  在RISC-V处理器上实现一个轻量级的Hypervisor。
  ☆12Updated 4 years ago
• luojia65 / tiaoshi-dashi-sbi
  调试大师：你见过最强的内核调试器
  ☆35Updated 3 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 2 years ago
• KuangjuX / hypocaust-2
  hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
  ☆55Updated last year
• rustsbi / fast-trap
  快速陷入处理
  ☆35Updated 2 months ago
• chyyuu / zCore-Design
  ☆13Updated 3 years ago
• chenzhiy2001 / code-debug
  Source-level operating system debugging tool that supports debugging kernel and multiple user processes synchronously. VSCode integration…
  ☆37Updated 2 weeks ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆34Updated 3 years ago
• rustsbi / slides
  All public report slides, articles and meeting minutes related to RustSBI
  ☆29Updated 3 weeks ago
• ISRC-CAS / tarsier-oerv
  Project magament for porting openEuler to RISC-V
  ☆34Updated last year
• Byte-OS / polyhal
  ☆17Updated this week
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• dramforever / opensbi-h
  WIP: A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆38Updated last month
• HUST-OS / design-pattern-notes
  各类内核的设计思路
  ☆19Updated 3 years ago
• xiyurain / UltraOS
  A Rust based Multicore OS developed by UltraTeam, HITsz. Currently updated on https://gitee.com/LoanCold/ultraos_backup
  ☆45Updated 10 months ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated last year
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• luojia65 / DailySchedule
  ☆23Updated 3 years ago
• KuangjuX / hypocaust
  hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.
  ☆48Updated 2 years ago
• stemnic / rustyvisor
  Hypervisor written in Rust for the RISC-V 1.0 hypervisor extension
  ☆16Updated 6 months ago
• MaxXSoft / GeeOS
  The Gee (寂) Operating System, written in YuLang.
  ☆34Updated 3 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆48Updated 5 months ago
• oscomp / proj1-rustsbi
  实现和扩展RISC-V SBI运行时，使之能够支持并运行操作系统
  ☆14Updated 3 weeks ago
• YdrMaster / rCore-Tutorial-in-single-workspace
  没分支的 rCore-Tutorial
  ☆45Updated 2 years ago
• OS-F-4 / usr-intr
  项目的主仓库
  ☆24Updated 2 years ago