cebarobot / UCAS-CALab-mycpu_axi_verify
计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15
☆12Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for UCAS-CALab-mycpu_axi_verify
- ☆25Updated 4 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Updated 4 years ago
- verification of simple axi-based cache☆17Updated 5 years ago
- Direct Access Memory for MPSoC☆12Updated 3 weeks ago
- CNN accelerator using NoC architecture☆15Updated 5 years ago
- EE577b-Course-Project☆15Updated 4 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆22Updated last year
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- ☆22Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- ☆9Updated 4 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated 5 months ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆11Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- YSYX RISC-V Project NJU Study Group☆11Updated 2 years ago
- The official NaplesPU hardware code repository☆11Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆13Updated 3 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- DMA controller for CNN accelerator☆12Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆44Updated 3 years ago
- A Verilog implementation of a processor cache.☆19Updated 6 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆21Updated 5 years ago
- ☆37Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆31Updated last year
- eyeriss-chisel3☆39Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆9Updated 4 years ago
- Verilog program☆11Updated 4 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Ratatoskr NoC Simulator☆21Updated 3 years ago