cebarobot / UCAS-CALab-mycpu_axi_verify
计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15
☆12Updated 4 years ago
Alternatives and similar repositories for UCAS-CALab-mycpu_axi_verify:
Users that are interested in UCAS-CALab-mycpu_axi_verify are comparing it to the libraries listed below
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Updated 5 years ago
- ☆25Updated 4 years ago
- Direct Access Memory for MPSoC☆12Updated 3 weeks ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- ☆24Updated 5 years ago
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- YSYX RISC-V Project NJU Study Group☆13Updated 2 weeks ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆22Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆27Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆14Updated 4 months ago
- Design and UVM-TB of RISC -V Microprocessor☆14Updated 6 months ago
- HLS code for Network on Chip (NoC)☆16Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated 7 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 9 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated 3 weeks ago
- AXI3 Bus Functional Models (Initiator & Target)☆27Updated 2 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆16Updated last year
- ☆9Updated 4 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- Custom Coprocessor Interface for VexRiscv☆10Updated 6 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- A Verilog implementation of a processor cache.☆23Updated 7 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆14Updated 5 years ago
- ☆12Updated 9 years ago
- Verilog program☆12Updated 4 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆47Updated 5 months ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated last month