计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15
☆22Dec 22, 2020Updated 5 years ago
Alternatives and similar repositories for UCAS-CALab-mycpu_axi_verify
Users that are interested in UCAS-CALab-mycpu_axi_verify are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆35Aug 11, 2021Updated 4 years ago
- 《CPU设计实战》学习记录及代码☆14Dec 30, 2023Updated 2 years ago
- 计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集☆18Aug 11, 2021Updated 4 years ago
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago
- ☆15Apr 18, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆57May 10, 2021Updated 5 years ago
- MIPS CPU☆14Dec 10, 2020Updated 5 years ago
- RackSched: A Microsecond-Scale Scheduler for Rack-Scale Computers☆24Oct 5, 2020Updated 5 years ago
- ☆22Jul 3, 2025Updated last year
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆150Jun 23, 2024Updated 2 years ago
- A 5-level pipelined MIPS CPU with branch prediction and great cache.☆19May 9, 2021Updated 5 years ago
- Direct Access Memory for MPSoC☆13Jun 16, 2026Updated 3 weeks ago
- Our repository for NSCSCC☆21Feb 22, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆16Nov 12, 2025Updated 7 months ago
- Deep SNNs with various neural coding methods (rate, phase, burst, TTFS)☆12Feb 15, 2022Updated 4 years ago
- ☆22Sep 26, 2025Updated 9 months ago
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆14Aug 1, 2023Updated 2 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 3 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Research Artifact for HPCA'24 Paper: *Modeling, Derivation, and Automated Analysis of Branch Predictor Security Vulnerabilities*.☆11Oct 30, 2025Updated 8 months ago
- ☆13Nov 13, 2022Updated 3 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆13Aug 26, 2024Updated last year
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头,使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后,在使用FAST计算图像特征点的同时,构建滑动窗口计算图像各个像素点的BRIEF描述符,完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配,最后…☆22Apr 16, 2025Updated last year
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆26Jun 30, 2025Updated last year
- ☆11Aug 4, 2022Updated 3 years ago
- A conda-smithy repository for memory_profiler.☆12Apr 22, 2026Updated 2 months ago
- risc-v 单周期和流水线cpu设计, 基于miniRV-1指令集,语言verilog☆11Feb 23, 2023Updated 3 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Cachebench, with hacks to make it run on SmartOS / x86.☆11Feb 15, 2012Updated 14 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- Instruction decoder microbenchmark suite☆11Oct 31, 2017Updated 8 years ago
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆11Oct 8, 2019Updated 6 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 11 years ago
- ☆12Mar 10, 2023Updated 3 years ago