Alternatives and similar repositories for matbi_fpga_season_1

Users that are interested in matbi_fpga_season_1 are comparing it to the libraries listed below

• semisgdh / SGDH-RVSoC
  An incredibly small 32-bit RISC-V rv32acim CPU capable of running Linux on FPGA, and software simulations.
  ☆22Updated 6 months ago
• Csuk0914 / dnn-rtl
  Verilog RTL Implementation of DNN
  ☆10Updated 6 years ago
• Ashwin-Rajesh / Verilog_projects
  Some beginner projects using verilog HDL, along with some documentation on basic syntax
  ☆11Updated 3 years ago
• ememos / GiantVM
  ☆9Updated 2 years ago
• yadav-sachin / Multilevel-Cache-Controller
  Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy.…
  ☆9Updated 4 years ago
• ucb-ee290c / fa18-smartnic
  SmartNIC
  ☆14Updated 6 years ago
• ConstantPark / Neural-Network-Acceleration-2
  Neural Network Acceleration using CPU/GPU, ASIC, FPGA
  ☆61Updated 4 years ago
• jaminthorns / cpu-cache-simulator
  A CPU cache simulator written in Python
  ☆29Updated 9 years ago
• ConstantPark / Nerual-Network-Acceleration-1
  Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM
  ☆52Updated 5 years ago
• jeonggunlee / Parallel_Programming
  Parallel Programming with CUDA @ Hallym University, 2019
  ☆16Updated 5 years ago
• fpgasystems / GPU-FPGA-Recommendation-System
  FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters
  ☆16Updated 4 years ago
• fpgasystems / FPGA-Recommendation-Accelerator
  MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions
  ☆16Updated 4 years ago
• kaist-cp / hazardflow
  HazardFlow: Modular Hardware Design of Pipelined Circuits with Hazards IMPORTANT: DON'T FORK!
  ☆19Updated 6 months ago
• ChenJianyunp / FPGA-Snappy-Decompressor
  A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.
  ☆22Updated last year
• AngeloJacobo / FPGA_Asynchronous_FIFO
  FIFO implementation with different clock domains for read and write.
  ☆13Updated 3 years ago
• slaclab / axi-pcie-core
  ☆21Updated this week
• opencis / opencis-core
  ☆9Updated this week
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆29Updated 6 years ago
• iamroot18 / 5.10
  리눅스 커널 v5.10/15 (iamroot 18차 소스분석용 - 230729 스터디 완주)
  ☆19Updated last year
• nqHITSZ / Systolic-Array
  course design
  ☆22Updated 7 years ago
• acsl-technion / ntl
  Networking Template Library for Vivado HLS
  ☆28Updated 4 years ago
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆42Updated 7 years ago
• uwsampl / lastlayer
  Towards Hardware and Software Continuous Integration
  ☆13Updated 4 years ago
• swsnu / aisys2023
  ☆100Updated last year
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆26Updated 5 years ago
• etri / nest-compiler
  NEST Compiler
  ☆116Updated 3 months ago
• gju06051 / TPU_HW_Verilog
  ☆14Updated 2 years ago
• snu-csl / pyrisc
  The Educational RISC-V Toolset in Python
  ☆37Updated 2 years ago
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆17Updated 5 years ago