Alternatives and similar repositories for matbi_fpga_season_1:

Users that are interested in matbi_fpga_season_1 are comparing it to the libraries listed below

• semisgdh / SGDH-RVSoC
  An incredibly small 32-bit RISC-V rv32acim CPU capable of running Linux on FPGA, and software simulations.
  ☆22Updated 3 months ago
• etri / nest-compiler
  NEST Compiler
  ☆116Updated last month
• yadav-sachin / Multilevel-Cache-Controller
  Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy.…
  ☆8Updated 4 years ago
• ConstantPark / Neural-Network-Acceleration-2
  Neural Network Acceleration using CPU/GPU, ASIC, FPGA
  ☆60Updated 4 years ago
• fpgasystems / FPGA-Recommendation-Accelerator
  MLSys 2021 paper: MicroRec: efficient recommendation inference by hardware and data structure solutions
  ☆16Updated 3 years ago
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆62Updated last year
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆46Updated 7 months ago
• Ashwin-Rajesh / Verilog_projects
  Some beginner projects using verilog HDL, along with some documentation on basic syntax
  ☆10Updated 3 years ago
• ucb-ee290c / fa18-smartnic
  SmartNIC
  ☆14Updated 6 years ago
• kaist-cp / shakeflow
  ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators (ASPLOS 2023)
  ☆52Updated last month
• umd-memsys / gem5
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆11Updated 4 years ago
• sjp38 / masim
  memory access workload simulator
  ☆21Updated 5 months ago
• mcrl / soff-compiler
  ☆29Updated 4 years ago
• ConstantPark / Nerual-Network-Acceleration-1
  Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM
  ☆51Updated 4 years ago
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
  ☆20Updated 2 months ago
• PSAL-POSTECH / M2NDP-public
  A Cycle-level simulator for M2NDP
  ☆24Updated 3 months ago
• kaist-cp / hazardflow
  HazardFlow: Modular Hardware Design of Pipelined Circuits with Hazards IMPORTANT: DON'T FORK!
  ☆14Updated 3 months ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆34Updated 10 years ago
• ngiambla / libmem
  ☆10Updated 2 years ago
• ChenJianyunp / FPGA-Snappy-Decompressor
  A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.
  ☆22Updated last year
• snu-csl / pyrisc
  The Educational RISC-V Toolset in Python
  ☆35Updated 2 years ago
• sangwoojun / bluedbm
  BlueDBM hw/sw implementation using the bluespecpcie PCIe library
  ☆11Updated 2 years ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆48Updated 3 months ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆29Updated 2 months ago
• CastLab-KAIST / OpenMDS
  ☆13Updated 2 years ago
• slaclab / axi-pcie-core
  ☆21Updated this week
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• fpgasystems / GPU-FPGA-Recommendation-System
  FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters
  ☆16Updated 3 years ago
• yuezuegu / sosa-compiler
  Repository for compilation and cycle-accurate simulator for scale-out systolic arrays
  ☆14Updated 2 years ago
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆17Updated 5 years ago