efabless / chipcraft---mest-course
☆33Updated 3 months ago
Alternatives and similar repositories for chipcraft---mest-course:
Users that are interested in chipcraft---mest-course are comparing it to the libraries listed below
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆65Updated last year
- ☆15Updated 2 years ago
- An overview of TL-Verilog resources and projects☆78Updated 3 weeks ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- ☆76Updated 3 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated last week
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆68Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆74Updated this week
- Introductory course into static timing analysis (STA).☆90Updated 5 months ago
- ☆40Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- SystemVerilog Tutorial☆138Updated 3 weeks ago
- This repo provide an index of VLSI content creators and their materials☆149Updated 8 months ago
- ☆154Updated 2 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆81Updated 8 months ago
- ☆12Updated 3 weeks ago
- ☆10Updated 2 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆125Updated 8 months ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆98Updated 8 months ago
- ☆16Updated 9 months ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated 10 months ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 5 months ago
- Verilog Fundamentals Explained for Beginners and Professionals☆21Updated 2 years ago
- Implementation of RISC-V RV32I☆17Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆68Updated this week