efabless / chipcraft---mest-courseLinks
☆36Updated 2 months ago
Alternatives and similar repositories for chipcraft---mest-course
Users that are interested in chipcraft---mest-course are comparing it to the libraries listed below
Sorting:
- This repo provide an index of VLSI content creators and their materials☆157Updated last year
- Curriculum for a university course to teach chip design using open source EDA tools☆109Updated last year
- SystemVerilog Tutorial☆172Updated 4 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆270Updated 3 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 3 years ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆140Updated 3 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated last year
- ☆13Updated 5 months ago
- An overview of TL-Verilog resources and projects☆82Updated 5 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆43Updated 3 years ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆164Updated last month
- Verilog/SystemVerilog Guide☆72Updated last year
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆99Updated last year
- 5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !☆12Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆19Updated 4 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆24Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆137Updated last month
- ☆166Updated 3 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 10 months ago
- Introductory course into static timing analysis (STA).☆97Updated 2 months ago
- Solve one design problem each day for a month☆46Updated 2 years ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆113Updated 3 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆116Updated 3 years ago
- ☆103Updated last month
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆94Updated 2 years ago
- ☆15Updated 2 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆79Updated last year