RISC-V RV32IMAFC Core for MCU
☆42Feb 1, 2025Updated last year
Alternatives and similar repositories for mmRISC-1
Users that are interested in mmRISC-1 are comparing it to the libraries listed below
Sorting:
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated this week
- Basic floating-point components for RISC-V processors☆11Aug 13, 2017Updated 8 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- ☆10Jun 9, 2022Updated 3 years ago
- Parasitic capacitance analysis of foundry metal stackups☆17Jan 12, 2026Updated last month
- 基于FPGA的PCIe 板卡,支持 离散量输入输出、ARINC429协议☆17Dec 1, 2022Updated 3 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated this week
- ☆22Jun 23, 2024Updated last year
- 32-bit soft RISCV processor for FPGA applications☆19Nov 25, 2023Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆27Jan 6, 2023Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆48May 10, 2024Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆27Feb 2, 2026Updated last month
- ☆21Jun 17, 2014Updated 11 years ago
- AHB3-Lite Interconnect☆109May 10, 2024Updated last year
- SystemVerilog & Verilog Module I/O parser and printer☆25Jul 25, 2021Updated 4 years ago
- ☆30Feb 15, 2026Updated 2 weeks ago
- Simple UVM environment for experimenting with Verilator.☆37Updated this week
- ☆28Jan 18, 2021Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Jun 27, 2022Updated 3 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆25Jul 17, 2025Updated 7 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆334Dec 2, 2025Updated 3 months ago
- submission repository for efabless mpw6 shuttle☆31Jan 10, 2024Updated 2 years ago
- A Verilog implementation of a processor cache.☆36Dec 29, 2017Updated 8 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- Zircon CPU in 2024☆11Nov 21, 2025Updated 3 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆13Feb 19, 2026Updated 2 weeks ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆14Dec 29, 2025Updated 2 months ago
- TOPPERSユーザーズフォーラム:ユーザのためのQ&Aおよび情報交換の場☆12Jun 16, 2022Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆60Updated this week
- A simple implementation of a UART modem in Verilog.☆175Nov 10, 2021Updated 4 years ago
- I2C models for cocotb☆41Sep 7, 2025Updated 5 months ago
- Platform Level Interrupt Controller☆46May 10, 2024Updated last year
- Python distributed lock with mongodb backend☆13Jun 11, 2023Updated 2 years ago
- 基于FPGA的FFT算法并行优化☆13Mar 7, 2024Updated last year
- Verification of an Asynchronous FIFO using UVM & SVA☆11Jun 26, 2025Updated 8 months ago
- Linux-3.14 kernel for RZ/A1☆10Oct 17, 2018Updated 7 years ago
- Comprehensive Pytest Cheatsheet☆15Mar 12, 2024Updated last year