saursin / riscv-atom
An open-source 32-bit RISC-V soft-core processor
☆32Updated 6 months ago
Alternatives and similar repositories for riscv-atom:
Users that are interested in riscv-atom are comparing it to the libraries listed below
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 3 weeks ago
- A simple DDR3 memory controller☆53Updated 2 years ago
- My notes for DDR3 SDRAM controller☆28Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated last month
- UART -> AXI Bridge☆60Updated 3 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆89Updated 3 weeks ago
- RISC V core implementation using Verilog.☆26Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆17Updated last year
- Open source ISS and logic RISC-V 32 bit project☆41Updated last month
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆61Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆22Updated 6 months ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- Platform Level Interrupt Controller☆35Updated 8 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆64Updated 9 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆44Updated last week
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆13Updated 11 months ago
- Neural Network accelerator powered by MVUs and RISC-V.☆12Updated 5 months ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆14Updated 3 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆32Updated this week
- RISC-V Nox core☆62Updated 5 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆24Updated 7 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆63Updated 2 years ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆51Updated 2 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆47Updated 5 months ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago