saursin / riscv-atomLinks
An open-source 32-bit RISC-V soft-core processor
☆33Updated last month
Alternatives and similar repositories for riscv-atom
Users that are interested in riscv-atom are comparing it to the libraries listed below
Sorting:
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆29Updated 4 years ago
- BlackParrot on Zynq☆41Updated 3 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆25Updated 3 years ago
- ☆30Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Platform Level Interrupt Controller☆40Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆46Updated last year
- General Purpose AXI Direct Memory Access☆50Updated last year
- RISC V core implementation using Verilog.☆26Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- RISC-V Nox core☆64Updated 2 months ago
- Open source ISS and logic RISC-V 32 bit project☆54Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆98Updated 3 weeks ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆71Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆62Updated 2 years ago
- ☆12Updated 2 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated last week
- Neural Network accelerator powered by MVUs and RISC-V.☆13Updated 10 months ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago
- Simple single-port AXI memory interface☆41Updated last year