An open-source 32-bit RISC-V soft-core processor
☆45Sep 1, 2025Updated 7 months ago
Alternatives and similar repositories for riscv-atom
Users that are interested in riscv-atom are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- A simple serial console utility☆17Jun 30, 2023Updated 2 years ago
- Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction☆12Apr 21, 2022Updated 3 years ago
- Minimal implementation of Raybox HDL ray caster concept☆27Nov 24, 2025Updated 4 months ago
- ☆14Mar 13, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 11 months ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 6 years ago
- VIP-Bench benchmarks for evaluating secure computation frameworks (e.g., HE, MPC, SE, etc...)☆13Jun 9, 2023Updated 2 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆31Jan 23, 2024Updated 2 years ago
- ☆13May 5, 2023Updated 2 years ago
- Pipelined 64-bit RISC-V core☆15Mar 7, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Nov 16, 2023Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆51Dec 18, 2025Updated 3 months ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆77May 15, 2023Updated 2 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Nov 1, 2020Updated 5 years ago
- Slides and material for Xilinx bootcamp☆22Aug 6, 2021Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆19Apr 27, 2024Updated last year
- ☆14May 27, 2023Updated 2 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Mar 18, 2026Updated 3 weeks ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Toy-Purpose TPU Simulator☆22Jun 7, 2024Updated last year
- git clone of http://code.google.com/p/axi-bfm/☆19May 21, 2013Updated 12 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆33May 26, 2024Updated last year
- Learn RISC-V☆22Dec 5, 2024Updated last year
- Ecmascript engine for C☆13Nov 14, 2020Updated 5 years ago
- A framework to make C memory safe☆13Sep 20, 2022Updated 3 years ago
- Ariane is a 6-stage RISC-V CPU☆155Dec 4, 2019Updated 6 years ago
- Spectre V1 Proof-of-Concept Attack in the Rust Language☆29Apr 3, 2025Updated last year
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆36Mar 27, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- CORE-V Family of RISC-V Cores☆348Mar 31, 2026Updated 2 weeks ago
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…☆17Jan 30, 2023Updated 3 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 5 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆111Mar 26, 2026Updated 3 weeks ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆13May 15, 2020Updated 5 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆102Jun 24, 2025Updated 9 months ago