saursin / riscv-atomView external linksLinks
An open-source 32-bit RISC-V soft-core processor
☆45Sep 1, 2025Updated 5 months ago
Alternatives and similar repositories for riscv-atom
Users that are interested in riscv-atom are comparing it to the libraries listed below
Sorting:
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- ☆13May 5, 2023Updated 2 years ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- ☆12Oct 8, 2025Updated 4 months ago
- Direct Access Memory for MPSoC☆13Jan 27, 2026Updated 2 weeks ago
- Matrix multiplication accelerator on ZYNQ SoC.☆12Apr 29, 2025Updated 9 months ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction☆12Apr 21, 2022Updated 3 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- A simple serial console utility☆17Jun 30, 2023Updated 2 years ago
- git clone of http://code.google.com/p/axi-bfm/☆19May 21, 2013Updated 12 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆19Apr 27, 2024Updated last year
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆76May 15, 2023Updated 2 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Feb 7, 2023Updated 3 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆27Jan 23, 2024Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆49Dec 18, 2025Updated last month
- Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.☆34Sep 17, 2024Updated last year
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆34Jan 12, 2026Updated last month
- Slides and material for Xilinx bootcamp☆22Aug 6, 2021Updated 4 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Jan 27, 2026Updated 2 weeks ago
- ☆25Feb 26, 2024Updated last year
- Open source ISS and logic RISC-V 32 bit project☆60Jan 20, 2026Updated 3 weeks ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Mar 29, 2024Updated last year
- ☆21Jun 17, 2014Updated 11 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Aug 14, 2024Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Nov 16, 2023Updated 2 years ago
- ☆33Nov 24, 2025Updated 2 months ago
- Systemverilog DPI-C call Python function☆28Mar 11, 2021Updated 4 years ago
- A Toy-Purpose TPU Simulator☆21Jun 7, 2024Updated last year
- Static Timing Analysis Full Course☆63Jan 14, 2023Updated 3 years ago
- 餐厅管理系统 - 练习JDBC、MySQL数据库、德鲁伊连接池的使用;用户登录、订座、点餐、结账、人事管理☆11Feb 22, 2022Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Dec 12, 2025Updated 2 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆26Jan 11, 2019Updated 7 years ago
- ☆28Jan 18, 2021Updated 5 years ago
- Architecting and Building High Speed SoCs, published by Packt☆29Jan 18, 2023Updated 3 years ago