saursin / riscv-atom
An open-source 32-bit RISC-V soft-core processor
☆31Updated 5 months ago
Related projects ⓘ
Alternatives and complementary repositories for riscv-atom
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆59Updated last month
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- ☆19Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆23Updated this week
- Pipelined RISC-V RV32I Core in Verilog☆36Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆68Updated 11 months ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- ☆10Updated 4 months ago
- RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.☆18Updated 2 years ago
- RISC V core implementation using Verilog.☆25Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆42Updated 3 weeks ago
- A simple DDR3 memory controller☆51Updated last year
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- ☆52Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆29Updated 5 months ago
- An open-source HDL register code generator fast enough to run in real time.☆36Updated this week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆40Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆36Updated 3 years ago
- Control and status register code generator toolchain☆105Updated 2 months ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago