saursin / riscv-atomLinks
An open-source 32-bit RISC-V soft-core processor
☆36Updated 2 months ago
Alternatives and similar repositories for riscv-atom
Users that are interested in riscv-atom are comparing it to the libraries listed below
Sorting:
- Open source ISS and logic RISC-V 32 bit project☆55Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 7 months ago
- Two Level Cache Controller implementation in Verilog HDL☆50Updated 5 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆104Updated 2 months ago
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- A simple DDR3 memory controller☆57Updated 2 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- ☆97Updated last year
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆102Updated 2 weeks ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆29Updated 4 years ago
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- General Purpose AXI Direct Memory Access☆54Updated last year
- RISC-V Nox core☆66Updated 4 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆72Updated 4 years ago
- Platform Level Interrupt Controller☆41Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- Basic RISC-V Test SoC☆138Updated 6 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆125Updated this week
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆23Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 weeks ago
- SystemVerilog Tutorial☆159Updated 2 months ago
- Simple cache design implementation in verilog☆49Updated last year
- RISC-V System on Chip Template☆158Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆87Updated this week
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆134Updated 3 years ago