Kobzon86 / Convolutional-Neural-Network-using-SystemVerilogLinks
Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
☆63Updated 10 months ago
Alternatives and similar repositories for Convolutional-Neural-Network-using-SystemVerilog
Users that are interested in Convolutional-Neural-Network-using-SystemVerilog are comparing it to the libraries listed below
Sorting:
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆47Updated this week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆65Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆105Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- ☆13Updated 5 months ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆115Updated 3 weeks ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆109Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- A 2D convolution hardware implementation written in Verilog☆48Updated 4 years ago
- Lecture about FIR filter on an FPGA☆12Updated last year
- Open source ISS and logic RISC-V 32 bit project☆57Updated 3 months ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆79Updated last year
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆16Updated 2 years ago
- SystemVerilog Tutorial☆170Updated 4 months ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- ☆41Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆76Updated 4 years ago
- 2D Systolic Array Multiplier☆20Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆47Updated last year
- Implementing Different Adder Structures in Verilog☆72Updated 6 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆82Updated last year
- This repo provide an index of VLSI content creators and their materials☆157Updated last year
- ☆103Updated 2 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 2 months ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆84Updated 3 months ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 8 months ago
- ☆42Updated 3 years ago