Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
☆67Nov 7, 2024Updated last year
Alternatives and similar repositories for Convolutional-Neural-Network-using-SystemVerilog
Users that are interested in Convolutional-Neural-Network-using-SystemVerilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DDA solver for the van der Pol oscillator using 16-bit posits☆28Jan 23, 2025Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 7 years ago
- FPGA digital camera controller and frame capture device in VHDL☆15Feb 11, 2013Updated 13 years ago
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆26Feb 24, 2026Updated 3 months ago
- Resources for my first book☆23Jun 21, 2023Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 6 years ago
- Verilog implementation of pipelined cpu☆13Feb 8, 2021Updated 5 years ago
- DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep lea…☆23Aug 13, 2025Updated 9 months ago
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆29Nov 21, 2020Updated 5 years ago
- ☆18Jul 9, 2025Updated 10 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆33Jun 27, 2022Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆94Nov 26, 2025Updated 6 months ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆18Feb 27, 2021Updated 5 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 9 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- CS4362 - Hardware Description Languages. Implemented SNN on an FPGA for real-time image processing using VHDL☆25Dec 29, 2023Updated 2 years ago
- TCL scripts for FPGA (Xilinx)☆36Jul 5, 2022Updated 3 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆20Aug 19, 2024Updated last year
- ☆22Sep 26, 2025Updated 8 months ago
- Cryptography accelerator core (for AES128/AES256 and SHA256) designed in Chisel3, primarily targeting ASIC platforms.☆10Jan 11, 2021Updated 5 years ago
- ☆48Apr 7, 2024Updated 2 years ago
- LEC - Logic Equivalence Checking - Formal Verification☆41Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆102Mar 29, 2024Updated 2 years ago
- ECE 3300 HDL Code☆63Jan 21, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- SGMII☆14Jul 17, 2014Updated 11 years ago
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- A convolutional neural network implemented in hardware (verilog)☆166Sep 7, 2017Updated 8 years ago
- Opensource DDR3 Controller☆437Jan 18, 2026Updated 4 months ago
- a mini 2x2 systolic array and PE demo☆72Dec 21, 2025Updated 5 months ago
- ☆46Apr 26, 2024Updated 2 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 3 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆128Dec 17, 2023Updated 2 years ago
- USB-PD-3.1-Verilog☆17Apr 22, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆64Nov 14, 2025Updated 6 months ago
- Project Peppercorn GateMate Test Cases☆16Feb 25, 2026Updated 3 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆55Apr 22, 2026Updated last month
- This repo provide an index of VLSI content creators and their materials☆170Aug 21, 2024Updated last year
- VHDL source file project for a hardware in the loop simulation of a permanen magnet motor with field oriented control design☆12Nov 22, 2022Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆27Apr 5, 2018Updated 8 years ago