Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
☆67Nov 7, 2024Updated last year
Alternatives and similar repositories for Convolutional-Neural-Network-using-SystemVerilog
Users that are interested in Convolutional-Neural-Network-using-SystemVerilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL-to-GDS: syn -> sta -> pnr -> gds☆15Sep 1, 2026Updated last month
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆30Nov 21, 2020Updated 5 years ago
- DDA solver for the van der Pol oscillator using 16-bit posits☆28Jan 23, 2025Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 7 years ago
- ☆25Aug 9, 2026Updated 2 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 7 months ago
- Verilog implementation of pipelined cpu☆13Feb 8, 2021Updated 5 years ago
- A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers☆10Jan 2, 2026Updated 9 months ago
- ☆49Apr 7, 2024Updated 2 years ago
- FPGA digital camera controller and frame capture device in VHDL☆15Feb 11, 2013Updated 13 years ago
- DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep lea…☆22Sep 11, 2026Updated last month
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 6 years ago
- VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers.☆19Oct 23, 2026Updated last week
- Curriculum for a university course to teach chip design using open source EDA tools☆179Oct 21, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Synopsys tools.☆16Jun 28, 2025Updated last year