Alternatives and similar repositories for VPV-Peripherals

Users that are interested in VPV-Peripherals are comparing it to the libraries listed below

• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆18Updated 7 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 6 months ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 12 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆44Updated 3 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆39Updated 3 weeks ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 5 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆83Updated 10 months ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆50Updated 9 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆42Updated 2 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 8 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆31Updated 9 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆24Updated 6 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 7 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆64Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆25Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆20Updated 4 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆65Updated 2 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated last year
• jianyicheng / HLS-benchmarks
  Benchmarks for High-Level Synthesis
  ☆10Updated 2 years ago