VP-Vibes / VPV-PeripheralsLinks
Library of example SystemC/TLM peripherals for various SoCs based on the SCS library
☆14Updated this week
Alternatives and similar repositories for VPV-Peripherals
Users that are interested in VPV-Peripherals are comparing it to the libraries listed below
Sorting:
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- RISC-V Virtual Prototype☆46Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆48Updated 3 weeks ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 4 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago
- Pulp virtual platform☆24Updated 5 months ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- Advanced Debug Interface☆14Updated 11 months ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- PCI Express controller model☆71Updated 3 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 2 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Hardware Verification library for C++, SystemC and SystemVerilog☆30Updated 13 years ago
- ☆33Updated 3 years ago
- Archives of SystemC from The Ground Up Book Exercises☆33Updated 3 years ago
- ☆13Updated 3 years ago