Alternatives and similar repositories for FlexiCAS

Users that are interested in FlexiCAS are comparing it to the libraries listed below

• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last month
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• arch-simulator-sig / simulator-paper
  ☆11Updated last year
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆45Updated 2 years ago
• miaochenlu / Gem5_tutorials
  ☆22Updated last month
• OSCPU / openperf
  ☆11Updated 10 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆21Updated 6 months ago
• HeliosXCore / HeliosXCore
  HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.
  ☆10Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 8 months ago
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆29Updated 2 years ago
• arch-simulator-sig / quard-star-tutorial-2021
  QuardStar Tutorial is all you need !
  ☆18Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 2 months ago
• NSCSCC-2022-TJU / ChiselMIPS
  第六届龙芯杯混元形意太极门战队作品
  ☆18Updated 3 years ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆13Updated 4 years ago
• OpenXiangShan / XSAI
  A fork of Xiangshan for AI
  ☆35Updated this week
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆28Updated last year
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆24Updated last month
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆17Updated last year
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆24Updated 7 months ago
• kuczmmar / Runahead
  Running ahead of memory latency - Part II project
  ☆10Updated 2 years ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 3 years ago
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆93Updated 2 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆50Updated last week
• yu-yake2002 / ysyx-docker
  A docker image for One Student One Chip's debug exam
  ☆10Updated 2 years ago
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆13Updated 2 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 3 years ago
• hanhwi / SimPoint
  ☆17Updated 3 years ago