Alternatives and similar repositories for FlexiCAS

Users that are interested in FlexiCAS are comparing it to the libraries listed below

• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 6 months ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆17Updated last week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• miaochenlu / Gem5_tutorials
  ☆20Updated this week
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• hanhwi / SimPoint
  ☆14Updated 3 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆42Updated 10 months ago
• observerw / ChiseLLM
  Reasoning LLMs optimized for Chisel code generation
  ☆16Updated last month
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆20Updated 2 months ago
• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆12Updated 4 months ago
• aakahlow / gem5Valid_Haswell
  ☆19Updated 5 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆57Updated last week
• miaochenlu / arch_sec_papers
  ☆15Updated 2 months ago
• ucb-bar / AuRORA
  Virtualized Accelerator Orchestration for Multi-Tenant Workloads
  ☆15Updated 6 months ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆31Updated 3 years ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated 8 months ago
• MaxXSoft / Bossa
  BOOM's Simulation Accelerator.
  ☆14Updated 3 years ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆19Updated 3 weeks ago
• iscas-tis / riscv-spec-core
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated this week
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆25Updated last year
• shinezyy / gem5-official-old
  ☆17Updated 3 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆34Updated 3 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated last month
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 2 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆28Updated 3 months ago
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated last year
• MaxXSoft / Frenda
  Split large FIRRTL into separated modules for incremental compilation.
  ☆10Updated 3 years ago
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆33Updated 3 years ago