Alternatives and similar repositories for Rabbit

Users that are interested in Rabbit are comparing it to the libraries listed below

• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆129Updated 3 months ago
• yhqiu16 / FDRA
  DRA+RISC-V Exploration Framework
  ☆16Updated last year
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆164Updated 5 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆113Updated 5 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆93Updated 2 weeks ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆103Updated 4 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆264Updated 9 months ago
• Buck008 / Transformer-Accelerator-Based-on-FPGA
  You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…
  ☆183Updated last year
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆77Updated 2 months ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆83Updated 6 months ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆27Updated 2 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆19Updated last year
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆190Updated 7 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆220Updated 2 years ago
• dldldlfma / super_small_toy_tpu
  ☆43Updated 4 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 4 months ago
• adervay1 / CIMulator
  a Computing In Memory emULATOR framework
  ☆13Updated last year
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆23Updated last year
• vickyiii / Quick-Start-Guide-for-HLS
  This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…
  ☆22Updated 2 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆46Updated 5 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆67Updated 3 years ago
• OSCPU / yosys-sta
  ☆78Updated 3 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• BIGWJZ / VLSI-DSP-Review
  ☆71Updated 5 years ago
• kerryliukk / NTHU-ICLAB
  清華大學 | 積體電路設計實驗 (IC LAB) | 110上
  ☆42Updated 2 years ago
• neurosim / DNN_NeuroSim_V1.4
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆73Updated 5 months ago
• SuperLiaoXH / SystolicArray-2D-FP16
  基于FP16的二维脉动阵列电路设计
  ☆11Updated 2 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆128Updated 5 years ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆123Updated 6 months ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆108Updated 5 years ago