Alternatives and similar repositories for Rabbit

Users that are interested in Rabbit are comparing it to the libraries listed below

• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆152Updated 8 months ago
• yhqiu16 / FDRA
  DRA+RISC-V Exploration Framework
  ☆18Updated 2 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆125Updated 5 months ago
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆109Updated 2 months ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆319Updated last year
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆124Updated 5 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆178Updated 6 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆114Updated 5 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆32Updated 3 years ago
• skycrapers / AM-Lib
  ☆30Updated 2 years ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆116Updated 11 months ago
• Buck008 / Transformer-Accelerator-Based-on-FPGA
  You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…
  ☆222Updated last year
• OSCPU / yosys-sta
  ☆89Updated last month
• kerryliukk / NTHU-ICLAB
  清華大學 | 積體電路設計實驗 (IC LAB) | 110上
  ☆47Updated 3 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆77Updated 3 years ago
• dldldlfma / super_small_toy_tpu
  ☆46Updated 4 years ago
• BIGWJZ / VLSI-DSP-Review
  ☆76Updated 5 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆22Updated last year
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 9 months ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆115Updated 5 years ago
• taoyilee / clacc
  Deep Learning Accelerator (Convolution Neural Networks)
  ☆196Updated 8 years ago
• Xilinx / xup_high_level_synthesis_design_flow
  AMD University Program HLS tutorial
  ☆123Updated last year
• vickyiii / Quick-Start-Guide-for-HLS
  This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…
  ☆26Updated 3 years ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆30Updated 2 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆180Updated 3 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆238Updated 2 years ago
• RV-BOSC / OpenNoC
  ☆215Updated 6 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆74Updated 2 months ago
• VCA-EPFL / FSA
  FSA: Fusing FlashAttention within a Single Systolic Array
  ☆84Updated 4 months ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆41Updated last year