Video Stream Scaler
☆41Jul 17, 2014Updated 11 years ago
Alternatives and similar repositories for video_stream_scaler
Users that are interested in video_stream_scaler are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- use Verilog HDL implemente bicubic interpolation in FPGA☆31Dec 31, 2019Updated 6 years ago
- ☆18Nov 28, 2017Updated 8 years ago
- Minimal DVI / HDMI Framebuffer☆85Aug 9, 2020Updated 5 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆32May 18, 2019Updated 6 years ago
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆15Feb 22, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Video compression systems☆24Jul 17, 2014Updated 11 years ago
- MIPI DSI controller☆85Jun 27, 2022Updated 3 years ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated last year
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- Implementation of an Artificial Neural Network (ANN) on FPGA using VHDL☆13Jun 22, 2016Updated 9 years ago
- Display ov7670 camera video on VGA monitors through Video DMA on ZedBoard☆19Jun 20, 2017Updated 8 years ago
- round robin arbiter☆78Jul 17, 2014Updated 11 years ago
- This repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog…☆38Mar 1, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Fork of OpenCores jpegencode with Cocotb testbench☆46Sep 5, 2015Updated 10 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 2 years ago
- Video and Image Processing☆40May 17, 2021Updated 4 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated last year
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- fpga i2c rtc oled based clock with alarm supports buzzer☆16May 15, 2021Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- ☆38Mar 10, 2021Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Nov 7, 2018Updated 7 years ago
- Documents for ARM☆40May 8, 2025Updated last year
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- AXI总线连接器☆105Mar 26, 2020Updated 6 years ago
- ☆24Apr 18, 2021Updated 5 years ago
- 100% Digital HDMI Board for use with the Original Xbox console. (Original Project Design by Ryzee119)☆38Mar 2, 2026Updated 2 months ago
- SDRAM controller with AXI4 interface☆104Aug 8, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆19Nov 20, 2017Updated 8 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- A hardware MJPEG encoder and RTP transmitter☆48Jan 15, 2020Updated 6 years ago
- My project for the course "Logic and Computer Design Fundamentals"(LCDF) in Zhejiang University☆12May 14, 2017Updated 8 years ago
- HiSilicon ip camera SoCs SystemRDL registers description☆12Oct 18, 2023Updated 2 years ago
- systemc建模相关☆27Jun 11, 2014Updated 11 years ago
- Hardware Viterbi Decoder in verilog☆31May 28, 2019Updated 6 years ago