freecores / video_stream_scalerLinks
Video Stream Scaler
☆40Updated 11 years ago
Alternatives and similar repositories for video_stream_scaler
Users that are interested in video_stream_scaler are comparing it to the libraries listed below
Sorting:
- use Verilog HDL implemente bicubic interpolation in FPGA☆29Updated 6 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- MIPI CSI-2 RX☆37Updated 4 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- ☆80Updated 3 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆19Updated 5 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆46Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆81Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- Gigabit Ethernet UDP communication driver☆80Updated 6 years ago
- ☆38Updated 10 years ago
- USB 2.0 Device IP Core☆73Updated 8 years ago
- A collection of phase locked loop (PLL) related projects☆115Updated 2 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆76Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- ☆28Updated 4 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- ☆33Updated 6 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆63Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆35Updated 6 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago