Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.
☆11Jan 15, 2022Updated 4 years ago
Alternatives and similar repositories for Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor
Users that are interested in Verilog-RS232-Synch-UART-RS232-Debugger-and-PC-host-RS232-Hex-editor are comparing it to the libraries listed below
Sorting:
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Feb 4, 2025Updated last year
- Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.☆18Feb 26, 2023Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆87Apr 8, 2024Updated last year
- ☆14Dec 15, 2017Updated 8 years ago
- YM-2149 / AY-3-8910 Complex Sound Generator FPGA core.☆34Jan 4, 2023Updated 3 years ago
- ☆12Oct 20, 2015Updated 10 years ago
- Gateware for the Terasic/Arrow DECA board, to become a USB2 high speed audio interface☆22Feb 28, 2022Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated last year
- RS-485 / CDBUS JPEG Camera☆19Updated this week
- Verilog clone of YM2149☆43Feb 1, 2025Updated last year
- A simple three-stage RISC-V CPU☆25May 4, 2021Updated 4 years ago
- AGRV2K裸奔测试工程☆29Jan 5, 2024Updated 2 years ago
- This repository, "Autonomous Driving System On Various Platforms", details the exploration and implementation of autonomous driving syste…☆10Aug 16, 2021Updated 4 years ago
- A device to control AXIOM cameras.☆33Feb 23, 2026Updated 2 weeks ago
- ☆14Jan 8, 2026Updated 2 months ago
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧，控制DA输出相应正弦信号☆10Jul 10, 2019Updated 6 years ago
- ☆10Nov 13, 2025Updated 3 months ago
- Tcp Server and Client Implementation with multiple client handling.☆12Jul 13, 2025Updated 7 months ago
- An Open Source driver for the IntelliKeys AT Keyboard☆13Oct 29, 2019Updated 6 years ago
- A winforms code generator for c#/sql/asp projects - simple, lightweight, and fast☆11Dec 23, 2025Updated 2 months ago
- A covenant for individuals who want to defend freedom☆17Oct 18, 2021Updated 4 years ago
- This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/☆11Aug 17, 2021Updated 4 years ago
- 基于Verilog实现的串口发送程序，带奇偶校验位。☆12Aug 23, 2019Updated 6 years ago
- Instrument to capture RSSI and data of 433MHz transmissions☆12Sep 5, 2020Updated 5 years ago
- ☆13Apr 12, 2023Updated 2 years ago
- IEEE 802.11 OFDM-based transceiver system☆43Dec 15, 2017Updated 8 years ago
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- ☆32Jan 11, 2026Updated last month
- Visual FTP client with dual-pane text-based UI for DOS and UNIX.☆18Dec 13, 2024Updated last year
- RT-Thread for MH1903☆10Jun 29, 2022Updated 3 years ago
- Example projects for the AlterNET Studio components suite.☆11Feb 6, 2026Updated last month
- Pure-Scala CRDTs☆11Jan 8, 2015Updated 11 years ago
- ☆13Updated this week
- Monkey Island fine-tune of Stable Diffusion☆12Dec 6, 2022Updated 3 years ago
- 基于.NET开发的WinForm自定义控件☆14Feb 23, 2024Updated 2 years ago
- Notes and utilities for reverse engineering Agilent PCIe Protocol Analyzers and their host software.☆14Oct 9, 2025Updated 5 months ago
- ☆13May 22, 2025Updated 9 months ago
- Winword 1 (Opus) build with protected mode compiler☆11Jun 7, 2024Updated last year
- Wrapper of libserialport written in V☆11Nov 21, 2021Updated 4 years ago