Mario-Hero / Async-Karin
Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
☆30Updated 4 years ago
Alternatives and similar repositories for Async-Karin:
Users that are interested in Async-Karin are comparing it to the libraries listed below
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Must-have verilog systemverilog modules☆33Updated 3 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- ☆59Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆81Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- A MCU implementation based PODES-M0O☆18Updated 5 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Implementation of the PCIe physical layer☆39Updated 3 months ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆37Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 5 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- Verilog Ethernet Switch (layer 2)☆43Updated last year
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆70Updated 11 months ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- ☆21Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago