Mario-Hero / Async-KarinLinks
Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
☆30Updated 4 years ago
Alternatives and similar repositories for Async-Karin
Users that are interested in Async-Karin are comparing it to the libraries listed below
Sorting:
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆70Updated 6 months ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- ☆79Updated 3 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆45Updated 2 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆51Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- Implementation of the PCIe physical layer☆57Updated 4 months ago
- AXI Interface Nand Flash Controller (Sync mode)☆97Updated last year
- Interface Protocol in Verilog☆50Updated 6 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆72Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- JPEG Encoder Verilog☆77Updated 3 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆82Updated 7 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆143Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆54Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- Ethernet 10GE MAC☆46Updated 11 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- Gigabit Ethernet UDP communication driver☆80Updated 6 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆46Updated 9 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆68Updated last year