Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
☆30Dec 14, 2020Updated 5 years ago
Alternatives and similar repositories for Async-Karin
Users that are interested in Async-Karin are comparing it to the libraries listed below
Sorting:
- ☆145Oct 3, 2020Updated 5 years ago
- A simple PDM microphone interface on FPGA☆14Jan 16, 2022Updated 4 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- ☆11Nov 24, 2020Updated 5 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- Wishbone SATA Controller☆24Oct 16, 2025Updated 4 months ago
- opensource crypto IP core☆29Nov 20, 2020Updated 5 years ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆14Dec 22, 2025Updated 2 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Dec 19, 2024Updated last year
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- DDR4 Simulation Project in System Verilog☆44Aug 18, 2014Updated 11 years ago
- Explanation of FPGA code for 8 PDM microphones in Matrix Creator☆16Nov 9, 2020Updated 5 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Jul 23, 2019Updated 6 years ago
- Open-Channel Open-Way Flash Controller☆22Sep 10, 2021Updated 4 years ago
- ☆28Jul 9, 2025Updated 7 months ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Jun 27, 2023Updated 2 years ago
- SERDES-based TDC core for Spartan-6☆18Aug 2, 2012Updated 13 years ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆136Sep 14, 2023Updated 2 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Jun 14, 2020Updated 5 years ago
- Xilinx AR65444 - Xilinx PCIe DMA Driver for linux☆21May 10, 2019Updated 6 years ago
- Verilog Implementation of SM4 s-box☆22Jun 24, 2019Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55May 10, 2021Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆84Oct 2, 2019Updated 6 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Jul 12, 2019Updated 6 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆61Oct 20, 2022Updated 3 years ago
- USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)☆59Jun 6, 2020Updated 5 years ago
- ☆35Dec 10, 2023Updated 2 years ago
- VSCode extension for enhancing verilog☆25Apr 27, 2024Updated last year
- An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII,用来…☆100Sep 14, 2023Updated 2 years ago
- Devotes to open source FPGA☆28May 9, 2020Updated 5 years ago
- A tiny example of PCM to PDM pipeline on FPGA☆22Feb 16, 2022Updated 4 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Mar 24, 2021Updated 4 years ago
- include hdlc (miao), 422 grapher, 1553b☆21Oct 10, 2019Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆33Oct 31, 2021Updated 4 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- Documents for ARM☆35May 8, 2025Updated 9 months ago
- Monitor ETW events for Windows process mitigation policies, with stack traces☆31Oct 7, 2022Updated 3 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆29Nov 9, 2015Updated 10 years ago