tsreaper / verilog-gobang-game-with-aiLinks
My project for the course "Logic and Computer Design Fundamentals"(LCDF) in Zhejiang University
☆12Updated 8 years ago
Alternatives and similar repositories for verilog-gobang-game-with-ai
Users that are interested in verilog-gobang-game-with-ai are comparing it to the libraries listed below
Sorting:
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆48Updated last year
- ☆34Updated 5 years ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated 11 months ago
- A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.☆20Updated 9 years ago
- Naïve MIPS32 SoC implementation☆115Updated 5 years ago
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 5 years ago
- Run rocket-chip on FPGA☆68Updated 7 months ago
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 5 years ago
- ☆18Updated 2 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…☆36Updated 3 years ago
- ☆31Updated 3 months ago
- ☆36Updated 6 years ago
- nscscc2018☆26Updated 6 years ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆43Updated 4 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆106Updated 6 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆24Updated 8 years ago
- An almost empty chisel project as a starting point for hardware design☆31Updated 5 months ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆43Updated 4 years ago
- FlaPGA Mario - A flappy-bird like video game implemented in Verilog for Basys3☆29Updated 6 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆28Updated 5 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 7 months ago
- Introduction to Computer Systems (II), Spring 2021☆51Updated 3 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- ☆169Updated 3 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆74Updated 7 months ago
- 中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程☆29Updated 5 years ago