tsreaper / verilog-gobang-game-with-aiLinks
My project for the course "Logic and Computer Design Fundamentals"(LCDF) in Zhejiang University
☆12Updated 8 years ago
Alternatives and similar repositories for verilog-gobang-game-with-ai
Users that are interested in verilog-gobang-game-with-ai are comparing it to the libraries listed below
Sorting:
- An almost empty chisel project as a starting point for hardware design☆32Updated 6 months ago
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆40Updated 7 years ago
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 5 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆29Updated 5 years ago
- Pick your favorite language to verify your chip.☆63Updated this week
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- CQU Dual Issue Machine☆37Updated last year
- Introduction to Computer Systems (II), Spring 2021☆51Updated 4 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 2 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆37Updated 3 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆63Updated 3 years ago
- The 'missing header' for Chisel☆21Updated 4 months ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆107Updated 6 years ago
- ☆67Updated 6 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 9 months ago
- ☆33Updated 4 months ago
- nscscc2018☆26Updated 6 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 5 years ago
- Run rocket-chip on FPGA☆70Updated 9 months ago
- Naïve MIPS32 SoC implementation☆115Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- ☆18Updated 2 years ago
- ☆78Updated 3 months ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆19Updated 2 months ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Updated last year