☆23Dec 7, 2019Updated 6 years ago
Alternatives and similar repositories for Digital_Front_End_Verilog
Users that are interested in Digital_Front_End_Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Devotes to open source FPGA☆28May 9, 2020Updated 6 years ago
- ☆15May 9, 2020Updated 6 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- ☆10Aug 30, 2024Updated 2 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK☆17Dec 9, 2018Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- Gaussian noise generator Verilog IP core☆35Jul 5, 2026Updated 4 months ago
- SPIFFS Bitstreamloader for the Spartan Edge Accelerator Board☆12May 22, 2020Updated 6 years ago
- ☆11Oct 10, 2019Updated 7 years ago
- ☆12Jul 4, 2019Updated 7 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- ☆12May 23, 2017Updated 9 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 6 years ago
- ☆20Aug 10, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- SEA-S7_gesture recognition☆17Aug 1, 2020Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆56Aug 12, 2017Updated 9 years ago
- SPI core☆12Jul 17, 2014Updated 12 years ago
- 🤖 An automated NTU Thesis LaTeX continuous integration and continuous deploying service built up with GitHub Actions.☆10May 8, 2020Updated 6 years ago
- commit rtl and build cosim env☆36Mar 29, 2024Updated 2 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 7 years ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- Verilog极简教程☆37Apr 7, 2019Updated 7 years ago
- rkv_v2x_addon☆12Aug 6, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 视频旋转（2019FPGA大赛）☆42May 5, 2020Updated 6 years ago
- asynchronous fifo based on verilog☆16Apr 14, 2022Updated 4 years ago
- 数字IC验证学习笔记：SV/UVM/AMBA总线（AXI/APB/AHB/AXI-Lite/AXI-Stream）+ 数字IC验证校招面经☆44Oct 17, 2026Updated 2 weeks ago
- Implementation of RSA algorithm on FPGA using Verilog☆27Aug 1, 2018Updated 8 years ago
- FIR implemention with Verilog☆51May 18, 2019Updated 7 years ago
- Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.☆15Feb 26, 2018Updated 8 years ago
- Asking questions about DBLP☆10Feb 6, 2026Updated 9 months ago
- ☆17Jul 21, 2017Updated 9 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆14Nov 1, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 8 years ago
- A Voila-Jones face detector hardware implementation☆33Nov 29, 2018Updated 7 years ago
- Deep Learning using Neural Network Toolbox + Finance Portfolio Selection with MorningStar☆10May 5, 2018Updated 8 years ago
- PolarDecoders implemented in Verilog. SC, SCL, CA-SCL and CA-PC-SCL are supported.☆10Sep 24, 2021Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/x393☆40Mar 16, 2023Updated 3 years ago
- LLVM-snippy random test generator☆18Updated this week
- fpga i2c slave verilog hdl rtl☆16Nov 26, 2015Updated 10 years ago