☆23Dec 7, 2019Updated 6 years ago
Alternatives and similar repositories for Digital_Front_End_Verilog
Users that are interested in Digital_Front_End_Verilog are comparing it to the libraries listed below
Sorting:
- Devotes to open source FPGA☆28May 9, 2020Updated 5 years ago
- ☆15May 9, 2020Updated 5 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Gaussian noise generator Verilog IP core☆32May 22, 2023Updated 2 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK☆16Dec 9, 2018Updated 7 years ago
- A variable FPGA-based QAM transmitter with scalable mixed time and frequency domain signal processing.☆22Jan 27, 2021Updated 5 years ago
- ☆19Aug 10, 2020Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Oct 8, 2020Updated 5 years ago
- ☆10Aug 30, 2024Updated last year
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- A Voila-Jones face detector hardware implementation☆33Nov 29, 2018Updated 7 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆28Aug 1, 2018Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34May 12, 2020Updated 5 years ago
- ☆31Feb 20, 2014Updated 12 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- FIR implemention with Verilog☆50May 18, 2019Updated 6 years ago
- 视频旋转（2019FPGA大赛）☆38May 5, 2020Updated 5 years ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- fpga i2c slave verilog hdl rtl☆16Nov 26, 2015Updated 10 years ago
- 🤖 An automated NTU Thesis LaTeX continuous integration and continuous deploying service built up with GitHub Actions.☆10May 8, 2020Updated 5 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- Verilog implementation of the SHA-512 hash function.☆44Jan 17, 2026Updated last month
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 8 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 3 years ago
- SPIFFS Bitstreamloader for the Spartan Edge Accelerator Board☆12May 22, 2020Updated 5 years ago
- 10小时搞定Latex排版☆12Jun 22, 2018Updated 7 years ago
- ☆12Sep 8, 2017Updated 8 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- ☆12May 23, 2017Updated 8 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago