Projects done for Advanced Digital Design with Verilog. Examples include code for applications like Sobel Edge Detection and DTMF generation.
☆12Sep 10, 2018Updated 7 years ago
Alternatives and similar repositories for Digital-Design-with-Verilog
Users that are interested in Digital-Design-with-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 基于Flask开发后端、VUE开发前端框架,在WEB端部署YOLOv5目标检测模型☆10Apr 29, 2024Updated last year
- Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board☆19Nov 17, 2021Updated 4 years ago
- Sobel–Feldman, Prewitt, Canny filter☆19Nov 9, 2019Updated 6 years ago
- This repository contains a SDSoC Project which includes an implementation of a 3-layered artificial neural network (testphase only). It c…☆12Oct 7, 2016Updated 9 years ago
- A program to predict the stock market. ML Algorithms: Random Forest, Decision Trees ans also a CNN (TensorFlow) were implemented and thei…☆19Dec 30, 2018Updated 7 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- ☆12Jun 22, 2023Updated 2 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated 11 months ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- 通信原理仿真☆21Apr 14, 2020Updated 5 years ago
- Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images☆67Nov 2, 2021Updated 4 years ago
- C Library for configuring the MCP3561/2/4 1/2/4 channel 24 Bit sigma-delta ADC on STM32☆20Oct 30, 2024Updated last year
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Jan 16, 2026Updated 2 months ago
- 基于yoloV3图像识别的商品结算系统☆20Jul 27, 2021Updated 4 years ago
- Implementation of Sobel Filter in Verilog☆25Mar 10, 2017Updated 9 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆13Jun 4, 2024Updated last year
- Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algor…☆26May 5, 2015Updated 10 years ago
- Igloo2 M2GL025 Creative Development Board☆11Oct 15, 2019Updated 6 years ago
- This is a SystemVerilog HDL implementation of Karatsuba multiplier.☆11Jul 8, 2020Updated 5 years ago
- Accelerating DNN inference and training on Zynq☆16Jul 22, 2020Updated 5 years ago
- ☆15Mar 15, 2020Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 5 years ago
- FPGA Verilog HDL design project (DE1-SoC)☆13Jan 19, 2018Updated 8 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 6 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated last year
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- ☆16Mar 27, 2024Updated last year
- Dr. Brian Gladman's XTS-AES implementation☆19Jun 8, 2020Updated 5 years ago
- A System Verilog/FPGA implementation of the Gigatron project.☆19Oct 29, 2018Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- A verilog HDL based project to control a servomotor with voice commands from an android phone.☆12Nov 11, 2019Updated 6 years ago
- 如何构建个人知识输出系统☆16Jul 6, 2016Updated 9 years ago
- Read-only mirror of https://framagit.org/tuxor1337/springerdownload. Pull requests and issues on GitHub cannot be accepted and will be au…☆41Feb 12, 2023Updated 3 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆23Nov 17, 2021Updated 4 years ago
- Testbenches for HDL projects☆23Updated this week