Alternatives and similar repositories for DeltaRNN:

Users that are interested in DeltaRNN are comparing it to the libraries listed below

• Intelligent-Microsystems-Lab / QuantizedLSTM
  Models and training scripts for "LSTMs for Keyword Spotting with ReRAM-based Compute-In-Memory Architectures" (ISCAS 2021).
  ☆14Updated 4 years ago
• AlexKly / Simple-Voice-Activity-Detector-using-MFCC-based-on-FPGA-Kintex
  Voice Activity Detector based on MFCC features and DNN model
  ☆19Updated last year
• ChFrenkel / ReckOn
  ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.
  ☆84Updated 3 years ago
• IA-C-Lab-Fudan / KWS-SoC
  This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
  ☆48Updated 4 years ago
• ahirsharan / LSTM
  Single Long Short Term Memory (LSTM) cell : Verilog Implementation
  ☆30Updated 4 years ago
• yiwangchunyu / AI-RISC
  Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects
  ☆14Updated 3 years ago
• dldldlfma / eyeriss_v1
  ☆12Updated 5 years ago
• RuokaiYin / MINT_Quantization
  MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award
  ☆13Updated last year
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆36Updated 5 years ago
• KULeuven-MICAS / snax_cluster
  A heterogeneous accelerator-centric compute cluster
  ☆14Updated this week
• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆33Updated 5 years ago
• nitheeshkm / sigmoid_tanh_verilog
  Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project
  ☆16Updated 5 years ago
• hsieh672 / SNN-Accelerator
  A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…
  ☆12Updated last year
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆48Updated 3 years ago
• neurosim / DNN_NeuroSim_V1.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network
  ☆42Updated 4 years ago
• neurosim / MLP_NeuroSim_V1.0
  Benchmark framework of synaptic device technologies for a simple neural network
  ☆27Updated 4 years ago
• adamsolomou / SC-DNN
  Stochastic Computing for Deep Neural Networks
  ☆31Updated 4 years ago
• eldrickm / wakey_wakey
  EE 272B - VLSI Design Project
  ☆11Updated 3 years ago
• open-neuromorphic / fpga-snntorch
  Notebooks and code for Neuromorphic Hardware Workshop at ISFPGA 2024.
  ☆46Updated last year
• IntelLabs / IntelNeuromorphicDNSChallenge
  Intel Neuromorphic DNS Challenge
  ☆144Updated 4 months ago
• rafamedina97 / FPGA_SNN_STDP
  FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks
  ☆35Updated 4 years ago
• arkhodamoradi / s2n2
  ☆17Updated 4 years ago
• coreylammie / TCAS-STDP
  IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures
  ☆26Updated 5 years ago
• Marco-Winzker / Spiking_NN_RGB_FPGA
  FPGA Design of a Spiking Neural Network.
  ☆38Updated 11 months ago
• UCLA-VAST / CLINK
  Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.
  ☆17Updated 5 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆32Updated last year
• niexun / LSTM
  LSTM neural network (verilog)
  ☆13Updated 6 years ago
• manoharvhr / PYNQ-Torch
  PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform
  ☆71Updated 4 years ago
• lamdangpham / ASIC--An_ASIC-Based_Architecture_of_Mel_Frequency_Cepstral_Coefficients
  ☆10Updated 2 months ago
• Angela-WangBo / Shenjing-RTL
  This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator
  ☆17Updated 5 years ago