TinyTapeout / tt-multiplexer

Related projects: ⓘ

• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆24Updated 3 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆30Updated 4 months ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆26Updated last week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆34Updated last year
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆51Updated 2 weeks ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆46Updated 8 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆31Updated 2 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 2 years ago
• grayresearch / s3ga
  S3GA: a simple scalable serial FPGA
  ☆10Updated last year
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆28Updated 7 months ago
• efabless / sky130_sram_macros_old
  ☆35Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• space-tudelft / cacd
  Space CACD
  ☆12Updated 4 years ago
• andylithia / Project-Yatsuhashi-Chip1
  ☆39Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• foshardware / lsc
  Libre Silicon Compiler
  ☆22Updated 3 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆33Updated 6 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆40Updated last month
• b224hisl / rioschip
  ☆31Updated last year
• sparrowgrine / prjtritium
  ☆22Updated 2 years ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆25Updated 3 weeks ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆21Updated 4 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆55Updated 2 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆76Updated 2 weeks ago
• PyFive-RISC-V / pyfive_top_202011
  Top level for the November shuttle
  ☆11Updated 2 years ago
• olofk / vidbo
  Virtual Development Board
  ☆57Updated 2 years ago