A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform Machine Learning models i.e. MLP Neural Networks on an FPGA using C, C++, Hardware Description Languages (HDL), High Level Synthesis (HLS) and Verilog.
☆22May 4, 2023Updated 3 years ago
Alternatives and similar repositories for Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA
Users that are interested in Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HDL implementation of a pipelined multilayer perceptron (neural network)☆17Sep 14, 2015Updated 11 years ago
- The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"☆12Oct 7, 2023Updated 3 years ago
- In this paper, a series of Ring Oscillators has been wired in different ways to form Ring Oscillator PUFs to find out the RO PUF which ha…☆12Jul 4, 2020Updated 6 years ago
- My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA☆13Jun 26, 2018Updated 8 years ago
- Use Verilog to design Arbiter PUF, then do Floorplan to make inter-variation approach 50%.☆14May 4, 2022Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ESP32-NOW with Wifi☆23Apr 11, 2025Updated last year
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 6 years ago
- [NeurIPS 2024] Advancing Training Efficiency of Deep Spiking Neural Networks through Rate-based Backpropagation☆20Jan 16, 2025Updated last year
- Implementation of ECC on FPGA-Zynq7000 SoC☆21Jul 12, 2019Updated 7 years ago
- Memory Compiler Tutorial☆14Aug 2, 2022Updated 4 years ago
- A Verilog implementation of a hand-written digit recognition Neural Network☆11Nov 16, 2024Updated last year
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆20Jan 28, 2022Updated 4 years ago
- Hardware Security Labs☆31May 3, 2017Updated 9 years ago
- "Low power" digital standard cells for SKY130 provided by SkyWater.☆11Apr 23, 2021Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Nov 27, 2025Updated 11 months ago
- An implemention of LSTM on FPGA based on Tensorflow☆10Mar 12, 2019Updated 7 years ago
- Machine Learning Techniques for Hardware Trojan Detection☆28Sep 24, 2020Updated 6 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 8 years ago
- Spiking Neural Network Accelerator☆15May 18, 2022Updated 4 years ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- Present Crypto Engine in Verilog☆13Feb 27, 2016Updated 10 years ago
- IO and periphery cells for SKY130 provided by SkyWater.☆14Nov 29, 2023Updated 2 years ago
- This is simply a binary neural network implemented on FPGA. The one and only functionality of this crap is to recognize handwritten digit…☆12Apr 20, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Hardware Description Language Translator☆17Oct 20, 2026Updated last week
- ☆14Nov 7, 2021Updated 4 years ago
- Senior Design☆13Jan 26, 2025Updated last year
- Software to look for interrelationships between constants and find formulas for number sequences☆19Jul 6, 2026Updated 3 months ago
- Ring Oscillator Physically Unclonable Funtion☆28Sep 9, 2021Updated 5 years ago
- ☆21Mar 25, 2026Updated 7 months ago
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆16Jun 3, 2021Updated 5 years ago
- Cache-accel: FPGA Accelerated Multi-Core Cache Simulator☆14Mar 12, 2022Updated 4 years ago
- Chisel RTL module of a unified ray tracer datapath pipeline. Supports ray-box intersection, ray-triangle intersection, acceleration for …☆16Jul 18, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆27Jul 21, 2025Updated last year
- BAG (BAG AMS Generator) Primitives Library for SKY130☆22May 16, 2023Updated 3 years ago
- A custom coprocessor and SoC for hardware security experiments in electronics.☆12May 20, 2017Updated 9 years ago
- A Python module to interact with an Intel JTAG UART☆17May 8, 2021Updated 5 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- MNIST classifier built for TensorFlow Lite - Android, iOS and other "lite" platforms☆40Apr 3, 2020Updated 6 years ago