Alternatives and similar repositories for pipelined-cpu-verilog

Users that are interested in pipelined-cpu-verilog are comparing it to the libraries listed below

• qmn / pershing
  An automatic place-and-route tool for Minecraft redstone circuits
  ☆25Updated 9 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• kagandikmen / TPU.sv
  Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1
  ☆18Updated 2 months ago
• Kenny2github / V2MC
  Synthesize Verilog to Minecraft redstone
  ☆16Updated 9 months ago
• merledu / SIngle-Cycle-RISC-V-In-Verilog
  This repository contains the verilog code files of Single Cycle RISC-V architecture
  ☆37Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 5 months ago
• rolandbernard / kleine-riscv
  A small and simple rv32i core written in Verilog
  ☆13Updated 3 years ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆50Updated 7 years ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆53Updated 2 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆59Updated 4 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• ducky64 / chisualizer
  Block-diagram style digital logic visualizer
  ☆23Updated 9 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• whitequark / bfcpu2
  A pipelined brainfuck softcore in Verilog
  ☆19Updated 11 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 5 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆29Updated last month
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 9 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated last month
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆145Updated 3 weeks ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆86Updated last year
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆22Updated 4 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated 2 weeks ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆21Updated 8 years ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆13Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆120Updated last month
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year