Resources for my first book
☆23Jun 21, 2023Updated 2 years ago
Alternatives and similar repositories for book1-zynq-intro
Users that are interested in book1-zynq-intro are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15Dec 1, 2022Updated 3 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆39Apr 13, 2026Updated 3 weeks ago
- ☆12Dec 22, 2020Updated 5 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 6 years ago
- FPGA (Verilog) implementation of the Flip01 8-bit processor.☆17Dec 30, 2024Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Control and Status Register map generator for HDL projects☆136May 24, 2025Updated 11 months ago
- ☆19May 4, 2026Updated last week
- Jupyter notebooks and Python utilities for power electronics analysis — EMC, magnetics optimization, impedance fitting☆13Mar 18, 2026Updated last month
- Tiny Tapeout GDS Action (using LibreLane)☆22Apr 26, 2026Updated 2 weeks ago
- TinyTapeout demo pcb's RP2040 functionality☆22Apr 8, 2026Updated last month
- FPGA digital camera controller and frame capture device in VHDL☆15Feb 11, 2013Updated 13 years ago
- ☆16Mar 18, 2024Updated 2 years ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆22Dec 11, 2023Updated 2 years ago
- ☆13Sep 22, 2022Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Single Cycle 32 bit MIPS☆20Dec 24, 2022Updated 3 years ago
- ☆17Apr 23, 2018Updated 8 years ago
- Where I keep all the Manim code I use for my videos☆20Sep 17, 2025Updated 7 months ago
- ☆13Aug 14, 2023Updated 2 years ago
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆84May 3, 2026Updated last week
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆67Nov 7, 2024Updated last year
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- Embedded Linux Basic☆12Sep 25, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆80Apr 11, 2022Updated 4 years ago
- Collection of some KiCad Libraries we use at MTE☆16Dec 26, 2020Updated 5 years ago
- Get Moving with Pynq on Alveo U50☆13Jul 13, 2020Updated 5 years ago
- The implement of <fast visibility restoration from a single color or gray level image>.☆11Mar 11, 2021Updated 5 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆73Feb 12, 2026Updated 2 months ago
- Open Logic FPGA Standard Library☆915Apr 29, 2026Updated last week
- ☆15Jul 3, 2024Updated last year
- FreeRTOS v9.0 Tutorial☆13May 2, 2017Updated 9 years ago
- A debugger / emulator for Ghidra☆14Oct 30, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆25Apr 27, 2023Updated 3 years ago
- An open-source HDL register code generator fast enough to run in real time.☆88Apr 27, 2026Updated 2 weeks ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆29Jul 10, 2024Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆33Aug 20, 2022Updated 3 years ago
- Use ECP5 JTAG port to interact with user design☆33Jul 23, 2021Updated 4 years ago
- Open Source MCU-Link CMSIS-DAP Debug probe for mobile robots (e.g. Pixhawk)☆19Feb 20, 2026Updated 2 months ago
- Official implementation of Inconsistency Masks. A robust semi-supervised segmentation framework that reframes model disagreement as a…☆19Jan 23, 2026Updated 3 months ago