der-mur / book1-zynq-introLinks
Resources for my first book
☆19Updated 2 years ago
Alternatives and similar repositories for book1-zynq-intro
Users that are interested in book1-zynq-intro are comparing it to the libraries listed below
Sorting:
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- ☆115Updated 2 years ago
- Verilog digital signal processing components☆163Updated 3 years ago
- An open-source HDL register code generator fast enough to run in real time.☆79Updated 3 weeks ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆193Updated 3 weeks ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆69Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 3 weeks ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 3 months ago
- Control and Status Register map generator for HDL projects☆128Updated 7 months ago
- A Python package to use FPGA development tools programmatically.☆143Updated 9 months ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆73Updated last month
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- 10G Low Latency Ethernet☆90Updated 2 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Drawio => VHDL and Verilog☆61Updated 2 years ago
- Control and status register code generator toolchain☆164Updated last month
- ☆15Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 10 months ago
- Slides and lab instructions for the mastering MicroBlaze session☆36Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆56Updated 6 years ago
- A collection of phase locked loop (PLL) related projects☆115Updated last year
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 7 months ago
- ☆29Updated 3 years ago
- A 2D convolution hardware implementation written in Verilog☆51Updated 5 years ago
- This repo provide an index of VLSI content creators and their materials☆162Updated last year
- Vitis Model Composer Examples and Tutorials☆113Updated 3 weeks ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- UART models for cocotb☆32Updated 3 months ago
- This repository contains some introductory level review about learning about FPGA Design including some tutorials, links to websites and …☆40Updated 9 months ago
- ☆47Updated last year