devindang / dv-cpu-rvLinks
A harvard architecture CPU based on RISC-V.
☆15Updated 2 years ago
Alternatives and similar repositories for dv-cpu-rv
Users that are interested in dv-cpu-rv are comparing it to the libraries listed below
Sorting:
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 11 months ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- ☆31Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 9 months ago
- ☆32Updated 3 weeks ago
- Platform Level Interrupt Controller☆43Updated last year
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆20Updated last month
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Updated last month
- ☆20Updated last week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 2 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- Advanced Architecture Labs with CVA6☆71Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆32Updated last week
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- RISC-V Core Local Interrupt Controller (CLINT)☆29Updated 2 weeks ago
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- The purpose of the repo is to support CORE-V Wally architectural verification☆16Updated last month
- IOPMP IP☆21Updated 5 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆71Updated 3 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated this week
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- A reliable, real-time subsystem for the Carfield SoC☆17Updated 2 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- APB Logic☆22Updated last month