devindang / dv-cpu-rvLinks
A harvard architecture CPU based on RISC-V.
☆15Updated 2 years ago
Alternatives and similar repositories for dv-cpu-rv
Users that are interested in dv-cpu-rv are comparing it to the libraries listed below
Sorting:
- ☆33Updated 2 months ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- ☆31Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Updated 11 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- Advanced Architecture Labs with CVA6☆73Updated 2 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- The official NaplesPU hardware code repository☆21Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆33Updated last year
- APB Logic☆23Updated last week
- SystemVerilog Functional Coverage for RISC-V ISA☆33Updated last month
- AXI3 Bus Functional Models (Initiator & Target)☆30Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆23Updated 10 months ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Updated 3 months ago
- Two Level Cache Controller implementation in Verilog HDL☆56Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆18Updated 2 months ago
- A reliable, real-time subsystem for the Carfield SoC☆18Updated 2 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated this week
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- BlackParrot on Zynq☆48Updated this week
- Simple single-port AXI memory interface☆49Updated last year