vickiegpt / computer-architecture-revisit-a-quantitative-approachLinks
This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine grained scheduling, map back to compiler, cross platform live migration and won't talk anything David Patterson's own work like RVV, TPU and deprecated X86
☆26Updated last year
Alternatives and similar repositories for computer-architecture-revisit-a-quantitative-approach
Users that are interested in computer-architecture-revisit-a-quantitative-approach are comparing it to the libraries listed below
Sorting:
- Yet another toy CPU.☆92Updated last year
- 《自己动手写AI编译器》☆28Updated 11 months ago
- ChocoPy LLVM Repo☆76Updated 2 years ago
- Recommended coding standard of Verilog and SystemVerilog.☆35Updated 3 years ago
- A scheduling framework for multitasking over diverse XPUs, including GPUs, NPUs, ASICs, and FPGAs☆112Updated last week
- Asynchronous semantics for architectural simulation and synthesis.☆49Updated this week
- Being a full-stack hacker, RISCV, LLVM, and more.☆18Updated 3 years ago
- The MOSAIC Operating Systems Model and Checker☆196Updated 2 years ago
- A toy compiler written in C++17 that translates SysY (a C-like toy language) into ARM-v7a assembly.☆143Updated 4 years ago
- Rebuild YatSenOS On RISC-V 64.☆21Updated 3 years ago
- MIT6.175 & MIT6.375 Study Notes☆43Updated 2 years ago
- Documentation for YatCPU☆53Updated last year
- Artifacts of EuroSys'24 paper "Exploring Performance and Cost Optimization with ASIC-Based CXL Memory"☆28Updated last year
- Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…☆71Updated last week
- ☆65Updated 2 years ago
- ngAP's artifact for ASPLOS'24☆24Updated 2 months ago
- Here is a final lab of Compiler in USTC, focusing on MLIR☆19Updated 4 years ago
- ☆20Updated 4 months ago
- MimiC is a compiler of C subset (extended SysY language) by USTB NSCSCC team.☆61Updated 2 years ago
- An optimizing compiler targeting armv7 and risc-v32☆61Updated 8 months ago
- 由HelloLLVM社区主席邱吉博士发起,联合HelloGCC等技术社区,推出了「南盘江计划」,致力于帮助更多的女性工程师在编译等基础软件领域实现个人职业目标。☆38Updated 2 months ago
- system paper reading notes☆247Updated last week
- My Paper Reading Lists and Notes.☆20Updated last week
- A Progam-Behavior-Guided Far Memory System☆35Updated last year
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆37Updated 3 years ago
- CXLMemSim: A pure software simulated CXL.mem for performance characterization☆168Updated this week
- BOOM's Simulation Accelerator.☆14Updated 3 years ago
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆57Updated last year
- Clio, ASPLOS'22.☆78Updated 3 years ago
- 💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…☆206Updated 5 years ago