Alternatives and similar repositories for blockwork:

Users that are interested in blockwork are comparing it to the libraries listed below

• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆27Updated last month
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆22Updated 3 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆30Updated this week
• mtdsousa / antlr4-verilog-python
  Generated files from ANTLR4 for Verilog parsing in Python
  ☆12Updated 2 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆29Updated last month
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆22Updated 4 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 2 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated last month
• tenthousandfailures / improving-constrained-random
  Implementation of a proposed method to improve constrained random simulation
  ☆16Updated 6 years ago
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆23Updated 2 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 5 months ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 4 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆116Updated 4 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆35Updated 3 weeks ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆57Updated 8 months ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆36Updated 9 years ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆55Updated last year
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆47Updated 8 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆35Updated 8 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆49Updated last week
• aignacio / cocotbext-ahb
  Cocotb AHB Extension - AHB VIP
  ☆13Updated 3 weeks ago
• svunit / svmock
  A mock framework for use with SVUnit
  ☆15Updated last year
• tudortimi / vpi
  SystemVerilog wrapper over the Verilog Programming Interface (VPI)
  ☆13Updated 2 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 7 months ago
• mxg / svx
  SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity
  ☆28Updated 6 months ago
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆16Updated 9 months ago