An opinionated build environment for EDA projects
☆19Jul 20, 2025Updated last year
Alternatives and similar repositories for blockwork
Users that are interested in blockwork are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Packed data structure specifications for multi-language hardware projects.☆17Jun 29, 2026Updated 4 months ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆61Sep 19, 2026Updated last month
- A Python package for creating and solving constrained randomization problems.☆20Oct 14, 2024Updated 2 years ago
- A Python package for creating and solving constrained randomization problems.☆20Oct 16, 2026Updated last week
- Making cocotb testbenches that bit easier☆43Feb 28, 2026Updated 8 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Open source RTL simulation acceleration on commodity hardware☆37Apr 13, 2023Updated 3 years ago
- ☆18Sep 29, 2026Updated last month
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- Dyno-IR Monorepo. High-Performance Compiler Framework for HW Synthesis & Beyond.☆17Updated this week
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- Python interface for cross-calling with HDL☆54Updated this week
- Yet Another Climbing Guide☆14Updated this week
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- Python bindings for slang, a library for compiling SystemVerilog☆67Jan 18, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- HDL-first mixed-signal co-simulation: embed ngspice circuits in Verilog through VPI☆76Sep 22, 2026Updated last month
- A tool for analysing the source-level static connectivity of a SystemVerilog design☆29Oct 7, 2026Updated 3 weeks ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- Staging area for new features of cocotb☆15Updated this week
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆18Feb 3, 2026Updated 8 months ago
- Provides types to specify how arguments are checked☆25Feb 17, 2019Updated 7 years ago
- SystemVerilog Linter based on pyslang☆34May 5, 2025Updated last year
- ☆10Nov 2, 2023Updated 2 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆36Oct 15, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An Emacs minor mode that highlights current word in all visible buffers☆13Jan 7, 2024Updated 2 years ago
- RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms☆20Sep 15, 2026Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆122Oct 16, 2026Updated last week
- example of python vpi integration☆13Nov 25, 2014Updated 11 years ago
- ☆15May 24, 2025Updated last year
- Python library for the SDS011 Air Quality Sensor☆14Oct 22, 2026Updated last week
- ☆10May 27, 2026Updated 5 months ago
- Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.☆24Dec 27, 2022Updated 3 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Useful tutorials and recipes for developers doing low-level work with the Graphcore IPU☆22Jun 29, 2022Updated 4 years ago
- An abstract model of EDA tool projects.☆14Oct 18, 2026Updated last week
- Репозиторий канала Verification For All☆16Oct 4, 2026Updated 3 weeks ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆53Jan 13, 2021Updated 5 years ago
- Coverview☆36Oct 5, 2026Updated 3 weeks ago
- Digital Design Express Course☆19Apr 11, 2019Updated 7 years ago
- Bazel build rules for compiling Verilog☆22Mar 4, 2024Updated 2 years ago