blockwork-eda / blockworkLinks
An opinionated build environment for EDA projects
☆19Updated 2 months ago
Alternatives and similar repositories for blockwork
Users that are interested in blockwork are comparing it to the libraries listed below
Sorting:
- Making cocotb testbenches that bit easier☆36Updated this week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆71Updated 2 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆126Updated last week
- Python bindings for slang, a library for compiling SystemVerilog☆63Updated 8 months ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆26Updated 7 months ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆117Updated this week
- Python interface for cross-calling with HDL☆36Updated 3 weeks ago
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Python-based IP-XACT parser☆137Updated last year
- SpiceBind – spice inside HDL simulator☆55Updated 3 months ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- SystemVerilog Linter based on pyslang☆31Updated 5 months ago
- SystemVerilog RTL Linter for YoSys☆21Updated 10 months ago
- SystemVerilog frontend for Yosys☆165Updated last week
- Control and status register code generator toolchain☆147Updated last week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 8 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆57Updated 2 weeks ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆63Updated last month
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆61Updated last week
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆47Updated 4 years ago
- ☆40Updated 10 years ago
- Python library for operations with VCD and other digital wave files☆53Updated 3 months ago
- Running Python code in SystemVerilog☆70Updated 3 months ago
- ideas and eda software for vlsi design☆50Updated last month
- ☆57Updated 9 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated 2 months ago
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Updated 6 months ago
- Implementation of post-process coverage, and batch waveform search☆16Updated 4 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Updated 3 weeks ago