Alternatives and similar repositories for blockwork

Users that are interested in blockwork are comparing it to the libraries listed below

• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆131Updated 3 weeks ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆73Updated 3 weeks ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated 10 months ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆27Updated last month
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆119Updated 2 months ago
• will-keen / constrainedrandom
  A Python package for creating and solving constrained randomization problems.
  ☆16Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆142Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆70Updated 2 months ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆165Updated last week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆156Updated last week
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated last week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆58Updated 3 weeks ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• tenthousandfailures / improving-constrained-random
  Implementation of a proposed method to improve constrained random simulation
  ☆17Updated 6 years ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 5 months ago
• alainmarcel / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…
  ☆26Updated 3 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 6 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 7 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆71Updated last week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 10 months ago
• chipsalliance / uvm-verilator
  ☆110Updated last month
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆37Updated last year
• edaa-org / pyEDAA.UCIS
  Unified Coverage Interoperability Standard (UCIS)
  ☆13Updated last week
• accellera / uvm
  ☆57Updated 9 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last week
• avidan-efody / wave_searcher
  Implementation of post-process coverage, and batch waveform search
  ☆17Updated 4 years ago