fallen / SucreLALinks
Open source Logic Analyzer based on LiteX SoC
☆25Updated last month
Alternatives and similar repositories for SucreLA
Users that are interested in SucreLA are comparing it to the libraries listed below
Sorting:
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆28Updated 10 months ago
- L öwe FPGA Board☆12Updated last year
- Firmware to implement USB communications on the CH32V307 microcontroller☆11Updated 2 years ago
- Test of a RP2040 PMOD attached to a LiteX SoC.☆25Updated 2 years ago
- Simplified environment for litex☆14Updated 4 years ago
- ☆23Updated 2 years ago
- CRUVI Standard Specifications☆19Updated last year
- Siglent SDS1x0xX-E FPGA bitstreams☆41Updated 5 months ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆17Updated last year
- WCH CH569 SerDes Reverse Engineering☆26Updated 2 years ago
- KiCad Library to make it easy to create both host boards and expansion boards and which are compatible with the Digilent "PMOD" specifica…☆39Updated 4 years ago
- LiteX based FPGA gateware for Thunderscope.☆25Updated last year
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- sump3 logic analyzer☆19Updated last month
- Kuchen Computer☆23Updated 11 months ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Updated last year
- Yet Another Debug Transport☆21Updated 3 years ago
- Container for compiling LiteX HDL FPGA designs using the free OpenXC7 tool chain and GitHub code spaces☆26Updated last year
- 2-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.☆19Updated 8 months ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆89Updated 6 months ago
- USB3 super speed development board useful as FPGA expansion based on WCH-Tech CH569☆26Updated 2 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- LiteX project for the ButterStick bootloader☆14Updated 2 years ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 3 weeks ago
- ☆12Updated 3 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆21Updated this week
- An FPGA reverse engineering and documentation project☆47Updated this week
- ☆22Updated 3 years ago