☆20Apr 10, 2014Updated 12 years ago
Alternatives and similar repositories for verilator
Users that are interested in verilator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog stuff and stuff.☆12Jun 2, 2016Updated 10 years ago
- SystemVerilog extension for Visual Studio Code☆14Dec 18, 2018Updated 7 years ago
- Open source RTL simulation acceleration on commodity hardware☆37Apr 13, 2023Updated 3 years ago
- SystemVerilog examples and projects☆21Jun 10, 2025Updated last year
- Minimal Forth interpreter for ARMv7 machines☆11Jul 26, 2017Updated 9 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 10 years ago
- Source code for the UoB Computer Science Society web portal☆14Updated this week
- Mach4 archived source.☆21Jun 7, 2024Updated 2 years ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Apr 6, 2023Updated 3 years ago
- Examples of how to Generate Schematics from SystemVerilog Synthesis Tools☆22Dec 22, 2023Updated 2 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆18Oct 27, 2012Updated 13 years ago
- ☆11Apr 18, 2026Updated 5 months ago
- ☆12May 8, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆23Feb 22, 2020Updated 6 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- A ray tracer implemented in C++ capable of rendering scenes described by a Lua based DSL. Developed as a project for the CS488 course.☆15Jul 24, 2015Updated 11 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- SymbiFlow WIP changes for Yosys Open SYnthesis Suite☆42Mar 19, 2024Updated 2 years ago
- Multi-way hypergraph partitioning algorithms: FMS (Fiduccia-Mattheyses-Sanchis), PLM (Partitioning by Locked Moves), PFM (Partitioning by…☆20Dec 27, 2025Updated 9 months ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆18Aug 11, 2026Updated last month
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Finding all the circuits of a directed graph with self-arcs and multiple-arcs by K.A. Hawick and H.A. James☆19Apr 11, 2013Updated 13 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- ☆19Jul 2, 2020Updated 6 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Download e-books from duxiu.com☆16Mar 26, 2015Updated 11 years ago
- iTerm2 is a terminal emulator for Mac OS X that does amazing things.☆17Apr 19, 2015Updated 11 years ago
- Generate JSON and HTML system call table for aarch64 from Linux source.☆11Mar 6, 2021Updated 5 years ago
- coursier CLI launchers☆16Sep 17, 2026Updated last week
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆13Oct 8, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- It is a fpga implementation of an i2c master, framebuffer for sdd1306 display☆12May 14, 2021Updated 5 years ago
- A library for working with QEMU qcow images☆20Oct 3, 2023Updated 2 years ago
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆14Jun 6, 2019Updated 7 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆47Jul 28, 2017Updated 9 years ago
- APB verification using UVM☆15Sep 7, 2026Updated 2 weeks ago
- The source code that empowers OpenROAD Cloud☆15Jun 29, 2020Updated 6 years ago
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated last year