Hardware Design, Exploration, and Code Generation for SoC Designers
☆12Dec 15, 2019Updated 6 years ago
Alternatives and similar repositories for blade
Users that are interested in blade are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Just A Really Very Impressive Systemverilog UVM Kit☆18Dec 17, 2020Updated 5 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- Medium Access Control layer of 802.15.4☆14Nov 14, 2014Updated 11 years ago
- JSON lib in Systemverilog☆44Feb 23, 2022Updated 4 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Jun 2, 2026Updated 3 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 4 months ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆74Nov 22, 2019Updated 6 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆26Jun 20, 2026Updated last week
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 7 months ago
- Code for the second edition of Advanced UVM.☆33Jan 28, 2017Updated 9 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆114Oct 31, 2023Updated 2 years ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- UVM interactive debug library☆36Feb 28, 2026Updated 4 months ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 6 years ago
- Mirror of Synopsys's Liberty parser library☆25Jul 6, 2018Updated 7 years ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated 2 years ago
- Useful UVM extensions☆28Jul 10, 2024Updated last year
- ☆24May 6, 2023Updated 3 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 6 years ago
- Yet Another Simulation Architecture☆81Sep 17, 2020Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆103Mar 29, 2024Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆26Oct 15, 2025Updated 8 months ago
- Download proccedings from DVCon☆24Mar 29, 2026Updated 3 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆146Jun 17, 2026Updated last week
- libView is a GUI tool for library file cell information view and comparison.☆27Jul 24, 2023Updated 2 years ago
- ☆17Jan 7, 2023Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆37Dec 24, 2024Updated last year
- Jude's vimrc for DV work(fine tuning for SV/UVM)☆21Mar 12, 2024Updated 2 years ago
- Systemverilog DPI-C call Python function☆28Mar 11, 2021Updated 5 years ago
- YAMM package repository☆34Mar 20, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and aut…☆37Oct 28, 2024Updated last year
- make your verilog DUT test more smart☆22Sep 9, 2016Updated 9 years ago
- singularity container for vnc desktop☆12Nov 8, 2020Updated 5 years ago
- CMake/GoogleTest/TravisCI/Coveralls/CoverityScan/Doxygen☆10Aug 8, 2019Updated 6 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- GUI for SymbiYosys☆17Oct 13, 2025Updated 8 months ago