aesc-silicon / elements-sdkLinks
Elements Software Development Kit
☆13Updated this week
Alternatives and similar repositories for elements-sdk
Users that are interested in elements-sdk are comparing it to the libraries listed below
Sorting:
- Virtual development board for HDL design☆42Updated 2 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆52Updated last week
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- USB virtual model in C++ for Verilog☆32Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated 5 months ago
- SpiceBind – spice inside HDL simulator☆56Updated 6 months ago
- Generate symbols from HDL components/modules☆22Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- SystemVerilog Linter based on pyslang☆31Updated 8 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- MMC (and derivative standards) host controller☆25Updated 5 years ago
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆26Updated 6 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆54Updated last week
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆13Updated 3 weeks ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆106Updated last week
- ☆27Updated 3 weeks ago
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- general-cores☆21Updated 5 months ago
- VHDL dependency analyzer☆24Updated 5 years ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Updated 4 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆31Updated this week
- VHDL plugin for RgGen☆15Updated this week
- sample VCD files☆40Updated 3 weeks ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆38Updated 7 years ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- Test dashboard for verification features in Verilator☆28Updated this week
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- A flexible and scalable development platform for modern FPGA projects.☆39Updated last month