Alternatives and similar repositories for vhdlref

Users that are interested in vhdlref are comparing it to the libraries listed below

• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 8 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆47Updated 3 years ago
• VHDL / news
  VHDL related news.
  ☆26Updated this week
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆28Updated 3 months ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆56Updated 3 months ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 8 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆74Updated this week
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆36Updated 2 weeks ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆51Updated this week
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆56Updated 3 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆30Updated 3 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆63Updated 4 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆47Updated last year
• schang412 / cocotbext-spi
  ☆26Updated 6 months ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆30Updated 9 months ago
• wzab / agwb
  Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems
  ☆12Updated 2 months ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated 2 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆116Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated last month
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆13Updated 2 months ago
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆37Updated last week