nobodywasishere / vhdlref

Related projects: ⓘ

• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆40Updated 2 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆25Updated 2 years ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆27Updated this week
• VHDL / news
  VHDL related news.
  ☆24Updated this week
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆31Updated 2 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆40Updated last week
• wavedrom / vcd-samples
  sample VCD files
  ☆36Updated 7 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆25Updated 6 months ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 4 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆28Updated 2 years ago
• rggen / rggen-vhdl
  VHDL plugin for RgGen
  ☆11Updated 3 months ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆21Updated 4 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆23Updated 4 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆26Updated 2 weeks ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• suoto / fpga_cores
  ☆32Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• CESNET / sphinx-vhdl
  ☆20Updated last month
• schang412 / cocotbext-spi
  ☆18Updated 2 months ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆28Updated this week
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 3 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆21Updated 9 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆40Updated last month
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆13Updated 5 months ago
• stnolting / wb_spi_bridge
  🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
  ☆21Updated 2 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆39Updated 8 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 3 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆19Updated 10 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 6 months ago