Alternatives and similar repositories for kv260_bringup

Users that are interested in kv260_bringup are comparing it to the libraries listed below

• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 5 months ago
• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆70Updated 3 years ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆109Updated 9 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆168Updated last week
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated 2 weeks ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated last week
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆60Updated this week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆43Updated 4 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• antmicro / kria-k26-devboard
  Open source AMD Xilinx Kria UltraScale+ SoM baseboard
  ☆46Updated 4 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆68Updated 9 months ago
• Digilent / digilent-vivado-scripts
  ☆69Updated 2 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆55Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆139Updated last week
• ATaylorCEngFIET / Xilinx_BootCamp
  Slides and material for Xilinx bootcamp
  ☆22Updated 3 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆72Updated 11 months ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆100Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• HDLForBeginners / Examples
  ☆93Updated last year
• efard / DSPHDL
  Digital Signal Processing and Well-Known Modulations on HDL
  ☆41Updated 2 weeks ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆71Updated 2 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆92Updated 4 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆54Updated last year
• ATaylorCEngFIET / Vitis_Hero
  ☆27Updated 3 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆86Updated 10 months ago
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆35Updated 2 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 5 months ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆32Updated 9 years ago