byuccl / tincr
A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite
☆39Updated 5 years ago
Alternatives and similar repositories for tincr:
Users that are interested in tincr are comparing it to the libraries listed below
- RapidSmith2 - the Vivado successor to RapidSmith. Released Jan 4, 2017.☆40Updated 5 years ago
- Running Python code in SystemVerilog☆68Updated 8 months ago
- FuseSoC standard core library☆130Updated 2 months ago
- Extensible FPGA control platform☆59Updated last year
- openHMC - an open source Hybrid Memory Cube Controller☆47Updated 8 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 10 months ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆36Updated 8 years ago
- Announcements related to Verilator☆39Updated 4 years ago
- SystemVerilog Development Environment☆53Updated 3 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆57Updated 3 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- Framework Open EDA Gui☆64Updated 3 months ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 6 months ago
- ☆26Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆57Updated 9 months ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆33Updated 4 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆53Updated last month
- ☆66Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆60Updated 3 weeks ago
- ☆31Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆63Updated 5 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated last month
- Hamming ECC Encoder and Decoder to protect memories☆31Updated 2 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 8 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆137Updated 2 years ago