ivanvig / 2dconv-FPGALinks
A 2D convolution hardware implementation written in Verilog
☆51Updated 5 years ago
Alternatives and similar repositories for 2dconv-FPGA
Users that are interested in 2dconv-FPGA are comparing it to the libraries listed below
Sorting:
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- Verilog RTL Design☆46Updated 4 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆67Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆71Updated last year
- AHB DMA 32 / 64 bits☆59Updated 11 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆128Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Updated 3 months ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- Structured UVM Course☆58Updated 2 years ago
- UART -> AXI Bridge☆70Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆58Updated 6 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆60Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆66Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Updated 6 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆50Updated 6 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- Verilog digital signal processing components☆170Updated 3 years ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆36Updated 3 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆86Updated 2 years ago
- DDR2 memory controller written in Verilog☆80Updated 13 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆33Updated 5 years ago