A 2D convolution hardware implementation written in Verilog
☆51Dec 21, 2020Updated 5 years ago
Alternatives and similar repositories for 2dconv-FPGA
Users that are interested in 2dconv-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementation of a 2D Convolutional Filter using VHDL for FPGAs.☆16Aug 21, 2022Updated 3 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆14Jul 23, 2020Updated 5 years ago
- Linux development repository for socfpga☆14Apr 1, 2026Updated last week
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆21May 27, 2024Updated last year
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆41Apr 13, 2021Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆21Dec 9, 2018Updated 7 years ago
- FMCW Radar verilog project☆35Jun 15, 2020Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- ☆14Mar 26, 2026Updated 2 weeks ago
- ☆25Apr 2, 2026Updated last week
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- Processor-FPGA transfer rate measurements in CycloneV-SoC☆15Nov 23, 2018Updated 7 years ago
- ☆17Sep 5, 2025Updated 7 months ago
- ☆14Apr 14, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 7 years ago
- Riegel Computer☆17Jun 30, 2023Updated 2 years ago
- Learn and build GPU RTL from scratch☆20Aug 1, 2025Updated 8 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆23Jul 6, 2018Updated 7 years ago
- Reusable image processing modules in SystemVerilog☆33Aug 7, 2017Updated 8 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- Computational Storage Device based on the open source project OpenSSD.☆31Oct 25, 2020Updated 5 years ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Leaninig OpenCV 学习笔记，源码。☆11Nov 23, 2018Updated 7 years ago
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 9 years ago
- Design of High-Level Synthesis of Xilinx FFT IP core via FFT library☆14Jul 17, 2023Updated 2 years ago
- ☆12Apr 7, 2020Updated 6 years ago
- ☆21Mar 7, 2025Updated last year
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆20Apr 15, 2022Updated 3 years ago
- Public repository of the data, scripts and methodology presented in the paper "Towards On-Board SAR Processing with FPGA Accelerators and…☆13Apr 12, 2023Updated 3 years ago
- 2D discrete cosine transform (DCT) of an 8x8 image in verilog HDL☆16Sep 2, 2022Updated 3 years ago
- KISCV, a KISS principle riscv32i CPU☆28Jan 11, 2025Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Examples of unions, interfaces, and assertions in SystemVerilog☆13Aug 31, 2013Updated 12 years ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆31May 18, 2019Updated 6 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆70Apr 14, 2024Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- Using Xilinx tools, the Unet architecture will be implemented and optimized for FPGA use. Some convolution-transposed conv sub-parts of t…☆18Feb 25, 2021Updated 5 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 2 months ago
- ☆11Jan 1, 2019Updated 7 years ago