ivanvig / 2dconv-FPGALinks
A 2D convolution hardware implementation written in Verilog
☆46Updated 4 years ago
Alternatives and similar repositories for 2dconv-FPGA
Users that are interested in 2dconv-FPGA are comparing it to the libraries listed below
Sorting:
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- Verilog RTL Design☆40Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆41Updated last year
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆84Updated last year
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- round robin arbiter☆74Updated 10 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- PYNQ Composabe Overlays☆73Updated last year
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆62Updated last year
- UART -> AXI Bridge☆61Updated 3 years ago
- ☆55Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- Asynchronous fifo in verilog☆35Updated 9 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆49Updated 5 years ago
- ☆34Updated 6 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆33Updated 6 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆85Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆76Updated last year
- Verilog for ASIC Design☆28Updated 3 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆43Updated 8 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago