ivanvig / 2dconv-FPGALinks
A 2D convolution hardware implementation written in Verilog
☆51Updated 5 years ago
Alternatives and similar repositories for 2dconv-FPGA
Users that are interested in 2dconv-FPGA are comparing it to the libraries listed below
Sorting:
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- Verilog RTL Design☆46Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆66Updated last year
- General Purpose AXI Direct Memory Access☆62Updated last year
- A simple DDR3 memory controller☆61Updated 3 years ago
- UART -> AXI Bridge☆69Updated 4 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Updated 2 months ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆128Updated 3 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆85Updated 2 years ago
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆61Updated 2 years ago
- AHB DMA 32 / 64 bits☆57Updated 11 years ago
- Structured UVM Course☆57Updated 2 years ago
- Interface Protocol in Verilog☆51Updated 6 years ago
- Repository gathering basic modules for CDC purpose☆57Updated 6 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆80Updated 2 weeks ago
- Lecture about FIR filter on an FPGA☆12Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆38Updated 3 years ago
- Verilog for ASIC Design☆31Updated 4 years ago
- round robin arbiter☆77Updated 11 years ago