System Verilog code describing a fully combinational binarized neural network.
☆36Jul 6, 2018Updated 8 years ago
Alternatives and similar repositories for combinational-bnn
Users that are interested in combinational-bnn are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆16Jan 18, 2025Updated last year
- OpenTitan FI formal verification framework☆16Aug 29, 2023Updated 2 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- [ICCV 2021] Code release for "Sub-bit Neural Networks: Learning to Compress and Accelerate Binary Neural Networks"☆33Jul 24, 2022Updated 4 years ago
- ☆10Aug 22, 2023Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆22May 27, 2024Updated 2 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆36Jun 30, 2020Updated 6 years ago
- PyTorch implementation of Local Binary Convolutional Neural Network http://xujuefei.com/lbcnn.html☆48Feb 18, 2020Updated 6 years ago
- Implementation of CNN using Verilog☆248Oct 13, 2017Updated 8 years ago
- Codes for Binary Ensemble Neural Network: More Bits per Network or More Networks per Bit?☆31Oct 7, 2019Updated 6 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Apr 2, 2018Updated 8 years ago
- Fully Hardware-Based Stochastic Neural Network☆23Jan 23, 2025Updated last year
- HLS code for a BNN accelerator☆17Sep 13, 2018Updated 7 years ago
- Proximal Mean-field for Neural Network Quantization☆21Apr 9, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 12 years ago
- ☆19Nov 14, 2022Updated 3 years ago
- An automated HDC platform☆11Mar 16, 2026Updated 4 months ago
- Jupyter notebook examples on image classification with quantized neural networks☆70May 5, 2020Updated 6 years ago
- low-level Capstone system bindings for Rust☆13Feb 15, 2019Updated 7 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53May 29, 2018Updated 8 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆51Jun 24, 2022Updated 4 years ago
- ☆10May 30, 2017Updated 9 years ago
- From Symbolic Logic Reasoning to Soft Reasoning: A Neural-Symbolic Paradigm☆12Jul 18, 2022Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆94Jul 3, 2019Updated 7 years ago
- ☆14Aug 8, 2022Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆30Jun 13, 2022Updated 4 years ago
- Based on the AberMUD V source code by Alan Cox☆10Nov 21, 2016Updated 9 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Quantized Neural Networks (QNNs) on PYNQ☆705Jan 4, 2022Updated 4 years ago
- Implementation for the paper "Latent Weights Do Not Exist: Rethinking Binarized Neural Network Optimization"☆76Dec 8, 2019Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆199Mar 20, 2024Updated 2 years ago
- We open-source our layout level fast EM simulation tool, EMSim, to the public.☆15Feb 8, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- ☆11Oct 7, 2023Updated 2 years ago
- Human Protein Atlas image classification competition☆13May 22, 2023Updated 3 years ago
- The code base for the I4 prototype, as described in the SOSP '19 paper "I4: Incremental Inference of Inductive Invariants for Verificatio…☆27May 25, 2021Updated 5 years ago
- Verilog Generator of Neural Net Digit Detector for FPGA☆312Sep 7, 2022Updated 3 years ago
- ☆16Jan 17, 2023Updated 3 years ago
- The robot base on ZedBoard☆16Jul 3, 2014Updated 12 years ago