Alternatives and similar repositories for hls-fpga-accelerators

Users that are interested in hls-fpga-accelerators are comparing it to the libraries listed below

• RakeshUIUC / multihead_attn_accelerator
  Accelerate multihead attention transformer model using HLS for FPGA
  ☆12Updated last year
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆52Updated 3 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆55Updated 3 months ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆17Updated 10 months ago
• booniebears / CoMN
  ☆18Updated last year
• lsq314 / SpMM_TCAD
  ☆17Updated 10 months ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆85Updated 3 years ago
• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆10Updated 4 months ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆45Updated 2 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆60Updated 4 months ago
• bonanyan / attentionlego
  Attentionlego
  ☆12Updated last year
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• fffasttime / AnyPackingNet
  ☆27Updated 3 months ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆49Updated last year
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• joaomiguelvieira / gem5-accel
  ☆9Updated last year
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆54Updated last week
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆75Updated 5 months ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆94Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆106Updated 5 years ago
• chiragsakhuja / spotlight
  ☆16Updated 2 years ago
• sfu-arch / SPAGHETTI
  RTL generator for SpGEMM
  ☆12Updated 4 years ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated last year
• sunxt99 / PIMCOMP-NN
  ☆65Updated 5 months ago
• neurosim / DNN_NeuroSim_V1.4
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆72Updated 4 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆81Updated 11 months ago
• hatsu3 / Sanger
  ☆49Updated 3 years ago