Alternatives and similar repositories for hls-fpga-accelerators

Users that are interested in hls-fpga-accelerators are comparing it to the libraries listed below

• KULeuven-MICAS / zigzag-llm
  Model LLM inference on single-core dataflow accelerators
  ☆10Updated 3 months ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆52Updated 3 years ago
• RakeshUIUC / multihead_attn_accelerator
  Accelerate multihead attention transformer model using HLS for FPGA
  ☆11Updated last year
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆16Updated 10 months ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• sjtu-zhao-lab / SALO
  An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences
  ☆27Updated last year
• fffasttime / AnyPackingNet
  ☆27Updated 2 months ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆53Updated 2 months ago
• chiragsakhuja / spotlight
  ☆16Updated 2 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆77Updated 3 years ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆56Updated 4 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆39Updated 2 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 2 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆53Updated last month
• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆17Updated 8 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆53Updated 2 months ago
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆16Updated 2 months ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆44Updated last year
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆66Updated 3 months ago
• Zhaoshixin-sky / CIM-MLC
  [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
  ☆37Updated last year
• SFU-HiAccel / HiSpMV
  [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS
  ☆12Updated 3 months ago
• hatsu3 / Sanger
  ☆45Updated 3 years ago
• bonanyan / attentionlego
  Attentionlego
  ☆12Updated last year
• lsq314 / SpMM_TCAD
  ☆17Updated 8 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 4 years ago
• abdelfattah-lab / BitMoD-HPCA-25
  ☆41Updated 5 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• gem5-X / TiC-SAT
  ☆16Updated 3 weeks ago
• gkrish19 / SIAM-Chiplet-based-Scalable-In-Memory-Acceleration-with-Mesh-for-Deep-Neural-Networks
  A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.
  ☆21Updated 11 months ago