ucb-bar / riscv-blas
Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V
☆17Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for riscv-blas
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- RISC-V Matrix Specification☆15Updated 2 months ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Support for Rocket Chip on Zynq FPGAs☆39Updated 5 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 3 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆22Updated last year
- ☆36Updated last week
- ☆42Updated 3 years ago
- Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension☆42Updated 3 years ago
- A polyhedral compiler for hardware accelerators☆56Updated 3 months ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- ☆15Updated 3 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- ☆78Updated 2 weeks ago
- Floating point modules for CHISEL☆28Updated 10 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆49Updated 4 years ago
- This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.☆11Updated 6 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆57Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated this week
- Chisel Cheatsheet☆31Updated last year
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- ☆21Updated last month
- The Shang high-level synthesis framework☆119Updated 10 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆52Updated 2 weeks ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆37Updated 2 weeks ago