KshitijLakhani / VLSI_Verilog_Projects
RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions, Control circuits like State Machines, and DSP applications like FFT.
☆13Updated 6 years ago
Alternatives and similar repositories for VLSI_Verilog_Projects:
Users that are interested in VLSI_Verilog_Projects are comparing it to the libraries listed below
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- ☆16Updated last year
- SystemVerilog examples and projects☆17Updated 6 years ago
- Architectural design of data router in verilog☆28Updated 5 years ago
- IEEE Executive project for the year 2021-2022☆8Updated 2 years ago
- AXI Interconnect☆47Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆32Updated 2 years ago
- ☆16Updated last year
- ☆16Updated 2 years ago
- Synchronous FIFO Testbench☆10Updated 2 years ago
- ☆16Updated 10 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- An 8 input interrupt controller written in Verilog.☆25Updated 12 years ago
- ☆38Updated 3 years ago
- RTL Verilog library for various DSP modules☆84Updated 2 years ago
- Implementation of the PCIe physical layer☆32Updated 2 weeks ago
- UVM and System Verilog Manuals☆39Updated 5 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆19Updated 10 months ago
- ☆17Updated 9 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆42Updated 10 months ago
- UART design in SV and verification using UVM and SV☆39Updated 5 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆9Updated 5 months ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆26Updated 5 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆47Updated 4 years ago
- To design test bench of the APB protocol☆16Updated 4 years ago
- ☆16Updated last year