KshitijLakhani / VLSI_Verilog_ProjectsLinks
RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions, Control circuits like State Machines, and DSP applications like FFT.
☆18Updated 6 years ago
Alternatives and similar repositories for VLSI_Verilog_Projects
Users that are interested in VLSI_Verilog_Projects are comparing it to the libraries listed below
Sorting:
- ☆47Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆63Updated 2 years ago
- ☆16Updated last year
- Architectural design of data router in verilog☆31Updated 5 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆31Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 11 months ago
- A collection of commonly asked RTL design interview questions☆31Updated 8 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆105Updated 3 years ago
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆70Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year
- System Verilog using Functional Verification☆12Updated last year
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆54Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆95Updated 2 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆60Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated 11 months ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆20Updated 2 months ago
- UVM and System Verilog Manuals☆44Updated 6 years ago
- A complete UVM TB for verification of single port 64KB RAM☆15Updated 4 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆20Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆19Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated last year
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆128Updated 4 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆48Updated 5 years ago
- UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.☆10Updated last year
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆106Updated 7 months ago