RegiaYoung / RISC-V-CPULinks
记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU
☆14Updated 4 years ago
Alternatives and similar repositories for RISC-V-CPU
Users that are interested in RISC-V-CPU are comparing it to the libraries listed below
Sorting:
- riscv指令集,单周期以及五级流水线CPU☆82Updated 8 months ago
- CPU Design Based on RISCV ISA☆122Updated last year
- 乱序双发处理器,在2024年计算机系统能力大赛CPU赛道(龙芯杯)获二等奖,全国第四☆16Updated last year
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆85Updated 5 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC(精简指令集)CPU(中央处理器)简单结构和Verilog实现。☆150Updated 6 years ago
- FPGA实现各种小游戏,学习并快乐着☆75Updated 3 years ago
- a simple riscv cpu☆22Updated 2 years ago
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9☆29Updated 4 years ago
- ☆84Updated 2 months ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- AXI协议规范中文翻译版☆163Updated 3 years ago
- Open IP in Hardware Description Language.☆26Updated 2 years ago
- Verilog实现单周期非流水线32位RISCV指令集(45条)CPU☆42Updated 4 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- ☆86Updated last week
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆53Updated last year
- ☆69Updated 9 years ago
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆27Updated last year
- ☆83Updated 5 months ago
- ARM中通过APB总线连接的UART模块☆67Updated 5 years ago
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆61Updated last year
- 一生一芯项目☆16Updated last year
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆11Updated 3 years ago
- AXI总线连接器☆104Updated 5 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆65Updated 3 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆57Updated last year
- 【2022集创赛】Arm杯一等奖作品:Cortex-M0智能娱乐收音机 开源项目☆28Updated 2 years ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆32Updated 3 years ago
- A simple RISC-V CPU written in Verilog.☆66Updated last year
- ☆70Updated 2 years ago