Alternatives and similar repositories for awesome-mpsoc

Users that are interested in awesome-mpsoc are comparing it to the libraries listed below

• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆63Updated 9 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆64Updated last year
• tomtor / HDL-deflate
  FPGA implementation of deflate (de)compress RFC 1950/1951
  ☆63Updated 6 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆60Updated 5 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 2 weeks ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 10 months ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆74Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆104Updated last year
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆31Updated last month
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆34Updated 7 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆34Updated 9 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated this week
• aeste / aemb
  Multi-threaded 32-bit embedded core family.
  ☆24Updated 13 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last month
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated last week
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆91Updated 6 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 6 years ago
• wtiandong / Hardware_circular_buffer_controller
  This is a circular buffer controller used in FPGA.
  ☆34Updated 9 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 7 months ago