Alternatives and similar repositories for awesome-mpsoc:

Users that are interested in awesome-mpsoc are comparing it to the libraries listed below

• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• pulp-platform / hyperbus
  ☆21Updated 2 months ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆23Updated 2 weeks ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆43Updated 9 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• hukenovs / tcl_for_fpga
  TCL scripts for FPGA (Xilinx)
  ☆31Updated 2 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆51Updated 3 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆91Updated 6 months ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆54Updated 3 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆37Updated 7 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆64Updated last month
• PeterAaser / tdt4255-chisel-intro
  ☆26Updated 4 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆40Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆38Updated 10 months ago
• wtiandong / Hardware_circular_buffer_controller
  This is a circular buffer controller used in FPGA.
  ☆33Updated 9 years ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆59Updated this week
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last month
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆30Updated 4 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 3 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆17Updated 4 months ago
• socrocket / core
  SoCRocket - Core Repository
  ☆35Updated 8 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last week
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago