Vitorian / awesome-mpsocLinks
Public resources available for Xilinx MPSOC+ and SDSOC hardware
☆18Updated 8 years ago
Alternatives and similar repositories for awesome-mpsoc
Users that are interested in awesome-mpsoc are comparing it to the libraries listed below
Sorting:
- Python interface to FPGA interchange format☆41Updated 2 years ago
- ☆26Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last week
- few python scripts to clone all IP cores from opencores.org☆22Updated last year
- SoCRocket - Core Repository☆37Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆82Updated 5 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆17Updated 6 months ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- Extensible FPGA control platform☆62Updated 2 years ago
- ☆18Updated 4 years ago
- Bitstream relocation and manipulation tool.☆46Updated 2 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- ☆10Updated last year
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated 9 months ago
- TCL scripts for FPGA (Xilinx)☆32Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated 9 months ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆55Updated 5 months ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆34Updated 3 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 4 years ago