Alternatives and similar repositories for SDC-AI-LectureNotes

Users that are interested in SDC-AI-LectureNotes are comparing it to the libraries listed below

• KHWeb19 / PersonalProject
  개인 프로젝트 저장소입니다.
  ☆7Updated 2 years ago
• KHWeb19 / LectureContents
  수업 자료는 모두 여기에 업로드 됩니다.
  ☆27Updated 2 years ago
• KHWeb19 / Homework
  과제는 여기에 제출합니다.
  ☆26Updated 2 years ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆221Updated last year
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆154Updated 5 months ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆198Updated this week
• Xilinx / Vitis-In-Depth-Tutorial
  ☆119Updated 3 years ago
• Xilinx / Vivado-Design-Tutorials
  ☆210Updated last month
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆39Updated 2 years ago
• Avnet / bdf
  Avnet Board Definition Files
  ☆133Updated last month
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆104Updated 2 years ago
• Xilinx / XilinxBoardStore
  ☆288Updated last week
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• EDDI-RobotAcademy / supplement-lecture
  웹/앱 보충 강의
  ☆13Updated 2 years ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆127Updated 6 months ago
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆217Updated 2 months ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆345Updated 4 months ago
• Xilinx / QNN-MO-PYNQ
  ☆247Updated 4 years ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆358Updated 2 weeks ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆87Updated 4 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆218Updated 7 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆262Updated last year
• HWAC-DL / hwac_object_tracker
  FPGA accelerated TinyYOLO v2 object detection neural network
  ☆72Updated 6 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆72Updated 11 months ago
• Xilinx / Vitis_Accel_Examples
  Vitis_Accel_Examples
  ☆540Updated 3 weeks ago
• roo16kie / MAC_Verilog
  Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .
  ☆12Updated 6 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆160Updated 5 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago