Alternatives and similar repositories for SDC-AI-LectureNotes

Users that are interested in SDC-AI-LectureNotes are comparing it to the libraries listed below

• KHWeb19 / LectureContents
  수업 자료는 모두 여기에 업로드 됩니다.
  ☆26Updated 3 years ago
• KHWeb19 / Homework
  과제는 여기에 제출합니다.
  ☆25Updated 3 years ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆234Updated 3 months ago
• Xilinx / XilinxBoardStore
  ☆306Updated 2 weeks ago
• Xilinx / Vitis_Accel_Examples
  Vitis_Accel_Examples
  ☆575Updated 2 weeks ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆156Updated 2 months ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆210Updated 2 months ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆117Updated 4 years ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆135Updated 2 weeks ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆48Updated 5 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆301Updated 2 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆369Updated this week
• Xilinx / Vivado-Design-Tutorials
  ☆237Updated 4 months ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆108Updated 3 years ago
• Avnet / bdf
  Avnet Board Definition Files
  ☆138Updated 2 months ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆332Updated 10 months ago
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆225Updated last year
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆108Updated 7 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆233Updated 8 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆90Updated 5 years ago
• Xilinx / PYNQ-BOT
  ☆30Updated 7 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆195Updated 3 years ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆372Updated 10 months ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆171Updated last year
• Xilinx / SDSoC-Tutorials
  SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials
  ☆155Updated 5 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆263Updated 12 years ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆347Updated this week
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆151Updated 7 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆433Updated last year