Xilinx / Kria-PYNQLinks
PYNQ support and examples for Kria SOMs
☆123Updated last year
Alternatives and similar repositories for Kria-PYNQ
Users that are interested in Kria-PYNQ are comparing it to the libraries listed below
Sorting:
- Kria Vitis platforms and overlays☆112Updated 8 months ago
- PYNQ Composabe Overlays☆74Updated last year
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆107Updated 3 years ago
- Board files to build Ultra 96 PYNQ image☆157Updated 4 months ago
- Vitis Model Composer Examples and Tutorials☆115Updated this week
- Avnet Board Definition Files☆140Updated 3 weeks ago
- ☆104Updated 2 years ago
- DPU on PYNQ☆241Updated 5 months ago
- Temporary repo to gather information about the Kria KV260 board☆76Updated 4 years ago
- ☆51Updated 4 years ago
- ☆312Updated this week
- ☆117Updated 4 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆86Updated 2 years ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆103Updated 6 years ago
- RISC-V Integration for PYNQ☆180Updated 6 years ago
- PYNQ Bootcamp 2019-2024 teaching materials.☆52Updated last year
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Updated 3 years ago
- ☆158Updated 3 weeks ago
- ☆30Updated 7 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆38Updated 4 years ago
- Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL☆75Updated 3 years ago
- AMD Xilinx University Program Vivado tutorial☆43Updated 2 years ago
- Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. …☆45Updated last year
- PYNQ-ZU, AUP UltraScale+ MPSoC academic board☆28Updated 3 months ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆170Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆66Updated last year
- This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL☆28Updated 4 years ago
- FOS - FPGA Operating System☆73Updated 5 years ago