gewuek / vitis_ai_custom_platform_flow
This project is trying to create a base vitis platform to run with DPU
☆47Updated 4 years ago
Alternatives and similar repositories for vitis_ai_custom_platform_flow:
Users that are interested in vitis_ai_custom_platform_flow are comparing it to the libraries listed below
- PYNQ Composabe Overlays☆70Updated 9 months ago
- Board files to build Ultra 96 PYNQ image☆154Updated 3 months ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- First lesson for you to use DNNDK, also it can be helpful for your AI learning☆68Updated last year
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- Zynq-7000 DPU TRD☆44Updated 5 years ago
- ☆65Updated 2 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆106Updated 4 years ago
- DPU on PYNQ☆211Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆56Updated 3 years ago
- ☆63Updated 6 years ago
- ☆122Updated 3 months ago
- FPGA/AES/LeNet/VGG16☆99Updated 6 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆71Updated 6 years ago
- ☆57Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆50Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆40Updated 2 years ago
- ☆44Updated 6 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 3 years ago
- round robin arbiter☆70Updated 10 years ago
- The second place winner for DAC-SDC 2020☆97Updated 2 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆51Updated 5 years ago