This project is trying to create a base vitis platform to run with DPU
☆49Jul 8, 2020Updated 6 years ago
Alternatives and similar repositories for vitis_ai_custom_platform_flow
Users that are interested in vitis_ai_custom_platform_flow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- For v1.2 test☆12Sep 5, 2020Updated 6 years ago
- DPU on PYNQ☆249Aug 12, 2025Updated last year
- ☆518Jan 16, 2026Updated 8 months ago
- ☆16Jan 20, 2021Updated 5 years ago
- ☆79Jul 27, 2022Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- meta-petalinux distro layer supporting Xilinx Tools☆105Jun 15, 2026Updated 3 months ago
- Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.☆1,807Feb 24, 2026Updated 7 months ago
- ☆141Jul 16, 2026Updated 2 months ago
- Board files to build Ultra 96 PYNQ image☆160Sep 14, 2025Updated last year
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Apr 11, 2020Updated 6 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆63Mar 27, 2025Updated last year
- Hybrid BFS on Xilinx Zynq☆18Jun 9, 2015Updated 11 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- Formerly known as the 'reVISION Getting Started Guide', the Embedded Reference Platforms User Guide covers the embedded vision reference …☆12Mar 22, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆120Feb 22, 2021Updated 5 years ago
- Tutorial for Vitis AI using the Sign Language MNIST☆17Apr 12, 2023Updated 3 years ago
- ☆12Apr 15, 2024Updated 2 years ago
- 2021 Xilinx China Winter Camp☆11Mar 12, 2021Updated 5 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator