sazczmh / Ultra96-PYNQ_A-simple-summary
Ultra96 PYNQ入门之一次简单的总结
☆14Updated 4 years ago
Alternatives and similar repositories for Ultra96-PYNQ_A-simple-summary
Users that are interested in Ultra96-PYNQ_A-simple-summary are comparing it to the libraries listed below
Sorting:
- ☆39Updated 6 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆51Updated 6 years ago
- Learn NVDLA by SOMNIA☆33Updated 5 years ago
- ☆23Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- ☆20Updated 3 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 4 years ago
- OpenDLA for trying the demo and FPGA solution☆16Updated 2 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- NVDLA small config implementation on Zynq ZCU104 (evaluation)☆23Updated 6 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- ☆45Updated 6 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆35Updated last month
- Convolution Neural Network of vgg19 model in verilog☆47Updated 7 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- Pynq computer vision examples with an OV5640 camera☆47Updated 5 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆31Updated last year
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆119Updated 2 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- Aiming at an AI Chip based on RISC-V and NVDLA.☆20Updated 7 years ago
- AIChip 2021 project, NCKU☆18Updated 4 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 3 years ago
- Digital Design Lab Spring 2019 Final Project☆11Updated 5 years ago
- This is an open CNN accelerator for everyone to use☆14Updated 5 years ago
- ☆65Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago