ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
☆19Updated 5 years ago
Alternatives and similar repositories for ZynqMP-FPGA-Ubuntu18.04-Ultra96:
Users that are interested in ZynqMP-FPGA-Ubuntu18.04-Ultra96 are comparing it to the libraries listed below
- Repository of HW design and SW for Ultra96 board + MIPI board☆17Updated 6 years ago
- HOG + SVM on FPGA☆26Updated 4 years ago
- ☆53Updated 2 years ago
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)☆130Updated last year
- 10G Ethernet MAC implementation☆21Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 5 months ago
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Updated 7 years ago
- ☆38Updated last year
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- Adding PR to the PYNQ Overlay☆17Updated 8 years ago
- Kria Vitis platforms and overlays☆99Updated last month
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- TCL scripts for FPGA (Xilinx)☆31Updated 2 years ago
- PYNQ-Z1 board files for Vivado☆34Updated 3 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆23Updated 6 years ago
- PCI Express controller model☆56Updated 2 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL☆69Updated 3 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆44Updated 2 weeks ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Zynq PR Management☆12Updated 9 years ago
- Basic Common Modules☆37Updated 5 months ago
- Demonstration of a video processing design for the Digilent Zybo, using Web Camera for input and VGA interface for output.☆25Updated 8 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆59Updated 4 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆59Updated last month
- Board files to build Ultra 96 PYNQ image☆154Updated 4 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- ☆24Updated 4 years ago