Alternatives and similar repositories for LectureContents

Users that are interested in LectureContents are comparing it to the libraries listed below

• KHWeb19 / Homework
  과제는 여기에 제출합니다.
  ☆25Updated 3 years ago
• EDDI-RobotAcademy / SDC-AI-LectureNotes
  It's for SDC-AI Lecture Notes
  ☆15Updated last year
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆228Updated 2 months ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆208Updated 3 weeks ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆157Updated last month
• Xilinx / Vivado-Design-Tutorials
  ☆230Updated 2 months ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆88Updated 5 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆117Updated 4 years ago
• Xilinx / Vitis_Accel_Examples
  Vitis_Accel_Examples
  ☆562Updated 2 months ago
• Xilinx / XilinxBoardStore
  ☆303Updated last week
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆48Updated 5 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆293Updated 3 weeks ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆132Updated 4 months ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆108Updated 2 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆226Updated 8 years ago
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆365Updated 9 months ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆168Updated last year
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆131Updated 7 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆35Updated 5 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆188Updated last year
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆330Updated 9 months ago
• Xilinx / Vitis-HLS-Introductory-Examples
  ☆731Updated 3 months ago
• Xilinx / PYNQ-BOT
  ☆29Updated 7 years ago
• HWAC-DL / hwac_object_tracker
  FPGA accelerated TinyYOLO v2 object detection neural network
  ☆74Updated 7 years ago
• Avnet / bdf
  Avnet Board Definition Files
  ☆135Updated last month
• Xilinx / PYNQ_Workshop
  ☆454Updated last year
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆173Updated 5 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆230Updated 2 years ago
• pp-Innovate / FPGA-ZynqNet
  FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
  ☆112Updated 8 years ago