9334swjtu / PYNQ_softmax
achieve softmax in PYNQ with heterogeneous computing.
☆63Updated 6 years ago
Alternatives and similar repositories for PYNQ_softmax:
Users that are interested in PYNQ_softmax are comparing it to the libraries listed below
- AXI总线连接器☆95Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆144Updated 5 years ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆146Updated last year
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆88Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆15Updated 6 years ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- AXI协议规范中文翻译版☆140Updated 2 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆184Updated last year
- ☆103Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆172Updated 11 months ago
- FPGA/AES/LeNet/VGG16☆95Updated 6 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆147Updated 4 months ago
- Deep Learning Accelerator (Convolution Neural Networks)☆176Updated 7 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆142Updated 8 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆90Updated 4 years ago
- IC Verification & SV Demo☆52Updated 3 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆79Updated 3 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆137Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆196Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆136Updated 3 weeks ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆135Updated 5 years ago
- An LeNet RTL implement onto FPGA☆41Updated 6 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆33Updated 2 years ago
- ☆124Updated 2 weeks ago
- IC implementation of Systolic Array for TPU☆197Updated 4 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 2 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆39Updated 7 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago