9334swjtu / PYNQ_softmax
achieve softmax in PYNQ with heterogeneous computing.
☆63Updated 6 years ago
Alternatives and similar repositories for PYNQ_softmax:
Users that are interested in PYNQ_softmax are comparing it to the libraries listed below
- AXI总线连接器☆97Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆97Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆154Updated 5 years ago
- upgrade to e203 (a risc-v core)☆42Updated 4 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- AXI DMA 32 / 64 bits☆111Updated 10 years ago
- AXI协议规范中文翻译版☆145Updated 2 years ago
- CNN accelerator implemented with Spinal HDL☆148Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆178Updated 7 years ago
- ☆107Updated 4 years ago
- IC Verification & SV Demo☆52Updated 3 years ago
- ARM中通过APB总线连接的UART模块☆64Updated 5 years ago
- ☆36Updated 4 years ago
- An LeNet RTL implement onto FPGA☆45Updated 6 years ago
- 数字IC秋招项目、手撕代码☆34Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆191Updated 2 years ago
- ☆144Updated 2 weeks ago
- achieve softmax in PYNQ with heterogeneous computing.☆15Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆143Updated last week
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- FPGA/AES/LeNet/VGG16☆102Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆148Updated 10 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆46Updated 8 months ago
- ☆61Updated 9 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆83Updated 3 years ago
- CPU Design Based on RISCV ISA☆105Updated 10 months ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆176Updated last year