achieve softmax in PYNQ with heterogeneous computing.
☆67Nov 1, 2018Updated 8 years ago
Alternatives and similar repositories for PYNQ_softmax
Users that are interested in PYNQ_softmax are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 5 years ago
- ☆153Mar 9, 2026Updated 7 months ago
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 8 years ago
- The demo of encoder and decoder in Matlab for EBCOT (Bit plane coder programmed by myself) and MQ coder. The MQ coder Matlab code is from…☆11Oct 18, 2016Updated 10 years ago
- This is a demo for still image compression application☆15Apr 14, 2018Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆12Jan 31, 2023Updated 3 years ago
- Source code repo for UVM Tutorial for Candy Lovers☆14Apr 23, 2017Updated 9 years ago
- ☆50Apr 8, 2023Updated 3 years ago
- 导向滤波算法——OpenGL实现☆11Jan 30, 2023Updated 3 years ago
- IMAGE PROCESSING ON XILINX PYNQ Z2 (CANNY, SOBEL)☆28Jan 17, 2022Updated 4 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Sep 23, 2026Updated last month
- ☆15Jun 27, 2024Updated 2 years ago
- ☆22Apr 23, 2025Updated last year
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆80Oct 9, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆10Feb 26, 2026Updated 8 months ago
- [FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heteroge…☆19Mar 6, 2021Updated 5 years ago
- Memory Compiler Tutorial☆15Oct 7, 2020Updated 6 years ago
- Python on Zynq FPGA for Convolutional Neural Networks☆624May 15, 2018Updated 8 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆43Mar 11, 2019Updated 7 years ago
- The second place winner for DAC-SDC 2020☆101Apr 23, 2022Updated 4 years ago
- A collection of research papers on efficient training of DNNs☆70Jul 6, 2022Updated 4 years ago
- Hardware Architecture for 30fps Full-HD Guided Image Filter☆12Jul 20, 2019Updated 7 years ago
- Human detection with HOG + SVM in MATLAB and Verilog, accelerated on a DE2-115 FPGA (0.757 ms, 54x faster than MATLAB)☆12Oct 16, 2026Updated 3 weeks ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- IC design and development should be faster，simpler and more reliable☆2,033Dec 31, 2021Updated 4 years ago
- 将 Verilog 设计规范、流水线模式与 FPGA 优化笔记结构化为可查询的本地知识库，供本地智能代理或脚本检索并返回带出处的实现建议与示例代码。☆28May 23, 2026Updated 5 months ago
- ☆14Dec 17, 2015Updated 10 years ago
- http://os.cs.tsinghua.edu.cn/research/undergraduate/zwpu2019☆12Jun 7, 2019Updated 7 years ago
- Official code of the paper "Learning to Reduce Information Bottleneck for Object Detection in Aerial Images"☆11Jul 31, 2023Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆187Dec 14, 2019Updated 6 years ago
- AXI总线连接器☆111Mar 26, 2020Updated 6 years ago
- ☆141May 30, 2026Updated 5 months ago
- RTL, Cmodel, and testbench for NVDLA☆2,195Mar 2, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 最小和算法实现☆10Jul 12, 2020Updated 6 years ago
- PYNQ学习资料☆179Nov 28, 2019Updated 6 years ago
- Verilog AXI components for FPGA implementation☆2,171Feb 27, 2025Updated last year
- ☆37May 29, 2021Updated 5 years ago
- Example Codes for Snorkeling in Verilog Bay☆17Sep 9, 2016Updated 10 years ago
- Open-source RTL IP developement for IIR/FIR filters in SystemVerilog, along with the C model and verification IP in UVM☆15Jul 8, 2026Updated 3 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆58May 10, 2021Updated 5 years ago