achieve softmax in PYNQ with heterogeneous computing.
☆68Nov 1, 2018Updated 7 years ago
Alternatives and similar repositories for PYNQ_softmax
Users that are interested in PYNQ_softmax are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 7 years ago
- This is a demo for still image compression application☆14Apr 14, 2018Updated 8 years ago
- Source code repo for UVM Tutorial for Candy Lovers☆14Apr 23, 2017Updated 9 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Jun 29, 2022Updated 3 years ago
- ☆151Mar 9, 2026Updated 2 months ago
- FPGA 同步FIFO与异步FIFO☆32Feb 26, 2019Updated 7 years ago
- IMAGE PROCESSING ON XILINX PYNQ Z2 (CANNY, SOBEL)☆27Jan 17, 2022Updated 4 years ago
- [FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heteroge…☆19Mar 6, 2021Updated 5 years ago
- Official code of the paper "Learning to Reduce Information Bottleneck for Object Detection in Aerial Images"☆11Jul 31, 2023Updated 2 years ago
- ☆15Jun 27, 2024Updated last year
- ☆48Apr 8, 2023Updated 3 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆184Dec 14, 2019Updated 6 years ago
- The second place winner for DAC-SDC 2020☆101Apr 23, 2022Updated 4 years ago
- ☆14Dec 17, 2015Updated 10 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆57May 10, 2021Updated 4 years ago
- AXI总线连接器☆106Mar 26, 2020Updated 6 years ago
- http://os.cs.tsinghua.edu.cn/research/undergraduate/zwpu2019☆12Jun 7, 2019Updated 6 years ago
- ☆47Aug 23, 2021Updated 4 years ago
- Example Codes for Snorkeling in Verilog Bay☆17Sep 9, 2016Updated 9 years ago
- ☆37May 29, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- System verilog register model for uvm testbenches.☆21Aug 29, 2018Updated 7 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Feb 22, 2021Updated 5 years ago
- IC设计中的一些经典书籍☆13Jul 28, 2020Updated 5 years ago
- Verilog AXI components for FPGA implementation☆2,037Feb 27, 2025Updated last year
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- FPGA☆160Jun 29, 2024Updated last year
- Courbariaux, Matthieu, Yoshua Bengio, and Jean-Pierre David. "Binaryconnect: Training deep neural networks with binary weights during pro…☆12Aug 31, 2020Updated 5 years ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Aug 6, 2013Updated 12 years ago
- 中文：☆109Nov 29, 2019Updated 6 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR☆23Oct 22, 2019Updated 6 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆19Oct 10, 2024Updated last year
- Structured Binary Neural Networks for Image Recognition☆16Oct 12, 2022Updated 3 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆92Sep 12, 2018Updated 7 years ago
- a project build the SSD net in pynq-z2☆15Aug 1, 2020Updated 5 years ago
- UVM candy lover testbench which uses YASA as simulation script☆17Apr 17, 2020Updated 6 years ago