mjosaarinen / lwaes_isaLinks
[HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
☆37Updated 4 years ago
Alternatives and similar repositories for lwaes_isa
Users that are interested in lwaes_isa are comparing it to the libraries listed below
Sorting:
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 2 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆59Updated 2 weeks ago
- HW Design Collateral for Caliptra RoT IP☆123Updated this week
- [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension☆29Updated last year
- ☆82Updated last year
- True Random Number Generator core implemented in Verilog.☆78Updated 5 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Updated last year
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- ☆89Updated 3 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- An open-source custom cache generator.☆34Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 months ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- RISC-V Configuration Structure☆41Updated last year
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆180Updated 7 months ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆23Updated 8 years ago
- ☆28Updated 9 months ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 9 months ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- ☆51Updated 2 months ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Updated 3 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆106Updated 4 years ago
- A Verilog Synthesis Regression Test☆37Updated last year